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Slide 56
Lab 3 – Internal Clock Source
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ICS’s seven modes of operation (continued)
FLL Bypassed External (FBE): In this mode the FLL is enabled
and controlled by an external reference clock, but it is bypassed.
The ICS supplies a clock derived from the external reference
clock.
FLL Bypassed External Low Power (FBELP): In this mode the FLL
is disabled and bypassed, and the ICS supplies a clock derived
from the external reference clock. The BDC clock is not available.
Stop: In stop mode the FLL is disabled and the internal or external
reference clocks can be selected to be enabled or disabled. The
BDC clock is not available and the ICS does not provide an MCU
clock source.
