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Slide 57
Lab 3 – Internal Clock Source
ICS Control Register 1
CLKS bits select the clock source that controls the bus frequency.
RDIV bits select the amount to divide down the FLL reference clock.
IREFS selects between using the internal reference clock (1) or an external
reference clock (0)
IRCLKEN enables (1) or disables (0) the internal reference clock for use as
ICSIRCLK
IREFSTEN controls whether the internal reference clock remains enabled (1)
or not (0) when the ICS enter stop mode
