Freescale Semiconductor MC68HC08KH12, Datasheet

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Advance Information MC68HC(7)08KH12
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Rev. 1.1
74
Freescale Semiconductor
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 7-9 shows interrupt entry timing. Figure
7-10 shows interrupt recovery timing.
Figure 7-9
.
Interrupt Entry
Figure 7-10. Interrupt Recovery
7.6.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
MODULE
IDB
R/W
INTERRUPT
DUMMY SP SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L
START ADDR
IAB
DUMMY PC – 1[7:0] PC – 1[15:8] X A CCR V DATA H V DATA L OPCODE
I BIT
MODULE
IDB
R/W
INTERRUPT
SP – 4 SP – 3 SP – 2 SP – 1 SP PC PC + 1 IAB
CCR A X PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
I BIT