Freescale Semiconductor MC68HC08KH12, Datasheet

Page: 153 / 262

MC68HC(7)08KH12
—
Rev. 1.1 Advance Information
Freescale Semiconductor
153
When the host computer has completed downloading code into the MCU
RAM, This code can be executed by driving PTA0 low while asserting
RST low and then high. The internal monitor ROM firmware will interpret
the low on PTA0 as an indication to jump to RAM, and execution control
will then continue from RAM. Execution of an SWI from the downloaded
code will return program control to the internal monitor ROM firmware.
Alternatively, the host can send a RUN command, which executes an
RTI, and this can be used to send control to the address on the stack
pointer.
The COP module is disabled in monitor mode as long as V
DD
+ V
HI
is
applied to either the IRQ1/V
PP
pin or the RST pin. ( See Section 7.
System Integration Module (SIM) for more information on modes of
operation.)
Table 10-2 is a summary of the differences between user mode and
monitor mode.
Table 10-2. Mode Differences
Modes
Functions
COP
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD
Monitor Disabled
(1)
1. If the high voltage (V
DD
+ V
HI
) is removed from the IRQ1/V
PP
pin or the RST pin, the SIM
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
$FEFE $FEFF $FEFC $FEFD $FEFC $FEFD