Advance Information
MC68HC(7)08KH12
—
Rev. 1.1
50
Freescale Semiconductor
NOTE:
The CONFIG register is a special register containing one-time writable
latches after each reset. Upon a reset, the CONFIG register defaults to
the predetermined settings as shown in
Figure 5-1
.
SSREC — Short stop recovery bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
COPRS — COP reset period selection bit
1 = COP reset cycle is (2
13
–2
4
)
×
CGMXCLK
0 = COP reset cycle is (2
18
–2
4
)
×
CGMXCLK
STOP — STOP instruction enable bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP disable bit
COPD disables the COP module.
See Section 13. Computer
Operating Properly (COP)
.
1 = COP module disabled
0 = COP module enabled
Address:
$001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
SSREC
COPRS
STOP
COPD
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 5-1. Configuration Register (CONFIG)
Summary of Contents for MC68HC08KH12
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