Freescale Semiconductor MC68HC08KH12, Datasheet

Page: 244 / 262

Advance Information MC68HC(7)08KH12
—
Rev. 1.1
244
Freescale Semiconductor
16.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See
7.8.3 Break Flag Control Register
(BFCR) and see the Break Interrupts subsection for each module.)
16.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
16.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
DD
+ V
HI
is present
on the RST pin.
16.5 Break Module Registers
Three registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)