Freescale Semiconductor M5407C3 User Manual Download Page 92

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B-6

M5407C3 User’s Manual

DIV6Q2.clk = DIV6Q1 ;

DA := !CS3_L & END16 & ENDIT & !IOCS16L & RD & !CLK8MHZ & SBHE #

!CS3_L & END8 & ENDIT & RD & !CLK8MHZ #

DLYDA & !CS3_L #

DA & !CS3_L;

DA.clk=XCLK0;

DLYDA :=!CS3_L & END16 & ENDIT & !IOCS16L & !RD & !CLK8MHZ & SBHE #

!CS3_L & END8 & ENDIT & IOCS16L & !RD & !CLK8MHZ #

!CS3_L & END8 & ENDIT & !SBHE & !RD & !CLK8MHZ ;

DLYDA.clk=XCLK0;

STARTISA := !CS3_L & !ENDIT ;

STARTISA.clk = CLK8MHZ ;

CBU43 (BCLK0,BCLK1,BCLK2,CLK8MHZ,STARTISA,!STARTISA)

BALE = STARTISA & !CLK8MHZ & !BCLK2 & !BCLK1 & !BCLK0 & !IOR & !IOW ;

IOR = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ & RD #

IOR & !CS3_L ;

IOW = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ & !RD #

IOW & STARTISA ;

END16 = !BCLK2 & BCLK1 & !BCLK0 & !CLK8MHZ#

END16 & STARTISA ;

END8 = BCLK2 & !BCLK1 & BCLK0 & !CLK8MHZ #

END8 & STARTISA ;

ENDIT = END16 & !IOCS16L & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & SBHE & STARTISA#

Freescale Semiconductor, Inc.

Summary of Contents for M5407C3

Page 1: ...M5407C3UM D Rev 1 1 8 2000 M5407C3 User s Manual Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 2: ...e Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorize...

Page 3: ...s returned properly packed and shipped prepaid to Matrix Design at address below Dated proof of purchase such as a copy of the invoice must be enclosed with the shipment We will return the shipment pr...

Page 4: ...for compliance with the limits for class a computing devices pursuant to Subpart J of Part 15 of FCC rules which are designed to provide reasonable protection against such interference Operation of th...

Page 5: ...7 1 9 1 Unpacking 1 7 1 9 2 Preparing the Board for Use 1 7 1 9 3 Providing Power to the Board 1 8 1 9 4 Selecting Terminal Baud Rate 1 8 1 9 5 The Terminal Character Format 1 8 1 9 6 Connecting the...

Page 6: ...Registers and Memory Map 3 4 3 1 9 Reset Vector Mapping 3 5 3 1 10 TA Generation 3 5 3 1 11 Wait State Generator 3 6 3 1 12 SDRAM DIMM 3 6 3 1 13 Flash ROM 3 7 3 1 14 JP15 Jumper and User s Program 3...

Page 7: ...h Number Title Page Number Contents vii PRELIMINAR WITHOUT NOTICE SDRAM MUX PAL Equation Appendix D Evaluation Board BOM Appendix E Schematics Appendix F Errata Freescale Semiconductor I Freescale Sem...

Page 8: ...viii M5407C3 User s Manual PRELIMINAR WITHOUT NOTICE CONTENTS Paragraph Number Title Page Number Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 9: ...d UM NEW 5407C3UMLOF fm 8 14 00 1 1 5407 Block Diagram 1 3 1 2 Minimum System Configuration 1 6 1 3 Pin assignment for female P4 Terminal connector 1 9 1 4 Jumper Locations 1 10 2 1 Flow Diagram of dB...

Page 10: ...ILLUSTRATIONS Figure Number Title Page Number x BookTitle PRELIMINAR WITHOUT NOTICE Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 11: ...8 14 00 1 1 Power Supply Connections 1 8 1 2 Jumper Settings 1 11 1 3 Jumper Settings 1 13 1 4 Jumper Settings 1 13 2 1 dBUG Command Summary 2 7 3 1 The M5407C3 Memory Map 3 5 3 2 J1 Connector Pin As...

Page 12: ...xii M5407C3 User s Manual PRELIMINAR WITHOUT NOTICE TABLES Table Number Title Page Number Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 13: ...Hardware Description The M5407C3 board provides the RAM Flash ROM on board NE2000 compatible Ethernet interface 10M bit sec RS232 and all the built in I O functions of the MCF5407 for learning and ev...

Page 14: ...4 bank selects to access all of the chips Therefore when using double sided DIMMs only half of the available memory will be accessible Since DIMMs are manufactured primarily for use in PCs the DQM si...

Page 15: ...Data Bus Control Signals addr 31 0 data 31 0 Control Signals PCI slot SDRAM 32bit 3 3V Module SDRAM External Mux PAL 1 RS232 drivers ColdFire MCF5407 Bus Clk Drv 26 pin debug connector 512KB Sync FSR...

Page 16: ...Communication Channels The MCF5407 has 2 built in UART s UART0 and UART1 with independent baud rate generators The signals of both channels are passed through external Driver Receivers to make the cha...

Page 17: ...k using signals REQ and GNT By default the controller currently has priority over the card in the equations in U18 if the user wanted to alter this priority they could do so by editing file ISA5407 ab...

Page 18: ...tem Configuration Figure 1 2 displays minimum system configuration Figure 1 2 Minimum System Configuration BDM Connector 7 0 to 14VDC Input Power dBUG RS 232 Terminal Or PC Freescale Semiconductor I F...

Page 19: ...tion One RS 232 communication cable One debug wiggler cable Programmers Reference Manual A selection of Third Party Developer Tools and Literature NOTE Avoid touching the mos devices Static discharge...

Page 20: ...e stop bit You need to insure that your terminal or PC is set to this format 1 9 6 Connecting the Terminal The board is now ready to be connected to a terminal Use the RS 232 male female DB 9 serial c...

Page 21: ...o parity one stop bit see section The Terminal Character Format Then select the baud rate as 19200 Now you are ready to apply power to the board Figur 1 3 shows pin assignments for female terminal con...

Page 22: ...1 10 M5407C3 User s Manual Installation And Setup Figure 1 4 Jumper Locations Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 23: ...level and current capability 1A and is connected to the board 2 Check that the terminal and board are set for the same character format and baud 3 Press the RESET button to insure that the board has...

Page 24: ...AA ON 0 Boot CS0 Auto Acknowledge AA DISABLED OFF 1 Boot CS AA Enabled with 15 wait states JP11 ON EVCC 3 3V Power to ColdFire MCF5407 I O JP12 ON IVCC 1 8V Power to ColdFire MCF5407 core JP13 ON Pul...

Page 25: ...OFF 2 3 8 col 13 row 2 3 2 3 2 3 OFF 9 col 13 row OFF 2 3 2 3 OFF 10 col 13 row 2 3 OFF 2 3 OFF 11 col 13 row Table 1 4 Jumper Settings Jumper Function JP251 1 The settings for JP25 and JP29 differ f...

Page 26: ...cable provided Freescale from P E Microcomputer Systems to the J5 connector No special setting is needed Refer to the ColdFire User s Manual BDM Section for additional instructions NOTE BDM functional...

Page 27: ...ides a self contained programming and operating environment dBUG interacts with the user through pre defined commands that are entered via the terminal These commands are defined in Section 2 4 Comman...

Page 28: ...es in one of the two basic modes If the command causes execution of the user program the dBUG firmware may or may not be re entered depending on the discretion of the user For the alternate case the c...

Page 29: ...ribed in detail in Chapter 1 This information is repeated here for convenience and to prevent possible damage 2 2 1 System Power up Be sure the power supply is connected properly prior to power up Mak...

Page 30: ...gram of dBUG Operational Mode 2 2 2 System Initialization The act of powering up the board will initialize the system The processor is reset and dBUG is invoked dBUG performs the following configurati...

Page 31: ...er to Section 1 10 System Power Up and Initial Operation Note the date xxx 199x xx xx xx may vary in different revisions Other means can be used to re initialize the M5407C3 Computer Board firmware Th...

Page 32: ...recognized as rub out keys for correcting typographical mistakes Command lines may be recalled using the Control U Control D and Control R key sequences Control U and Control D cycle up and down throu...

Page 33: ...lp command Help IRD ird module register Internal Register Display IRM irm module register data Internal Register Modify LR lr width addr Loop Read LW lw width addr data Loop Write MD md width begin en...

Page 34: ...mbly If valid the new assembly is placed into memory and the address incremented accordingly If the assembly is not valid then memory is not modified and an error message produced In either case memor...

Page 35: ...ntical the address of the first mismatch is displayed The value for addresses addr1 and addr2 may be an absolute address specified as a hexadecimal value or a symbol name The value for length may be a...

Page 36: ...l This command first aligns the starting address for the data access size and then increments the address accordingly during the operation Thus for the duration of the operation this command performs...

Page 37: ...cified as hexadecimal values or symbol names If the destination address overlaps the block defined by begin and end an error message is produced and the command exits Examples To copy a block of memor...

Page 38: ...int is encountered during the execution of target code the count value is compared against the trigger value If the count value is equal to or greater than the trigger value a breakpoint is encountere...

Page 39: ...the address accordingly during the operation Thus for the duration of the operation this command performs properly aligned memory accesses Examples To search for the 16 bit value 0x1234 in the memory...

Page 40: ...If an absolute value passed into the DC command is prefixed by 0x then data is interpreted as a hexadecimal value Otherwise data is interpreted as a decimal value All values are treated as 32 bit qua...

Page 41: ...ore meaningful disassembly This is especially useful for branch target addresses and subroutine calls The DI command attempts to track the address of the last disassembled opcode If no address is prov...

Page 42: ...ation address of each S record is adjusted by offset The DL command checks the destination download address for validity If the destination is an address outside the defined user space then an error m...

Page 43: ...Default filename and filetype parameters are manipulated using the SET and SHOW commands The DN command checks the destination download address for validity If the destination is an address outside t...

Page 44: ...fined breakpoints are inserted into the target code and the context is switched to the target program Control is only regained when the target code encounters a breakpoint illegal instruction trap 15...

Page 45: ...d as a hexadecimal value or a symbol name When the GT command is executed all breakpoints are inserted into the target code and the context is switched to the target program Control is only regained w...

Page 46: ...egister is located and register refers to the specific register to display The registers are organized according to the module to which they belong The available modules on the MCF5407 are CS DMA0 DMA...

Page 47: ...to modify The data parameter specifies the new value to be written into the register The registers are organized according to the module to which they belong The available modules on the MCF5407 are C...

Page 48: ...he address of where user code may start is given If command is provided then a brief listing of the syntax of the specified command is displayed Examples To obtain a listing of all the commands availa...

Page 49: ...the data at addr until a key is pressed The optional width specifies the size of the data to be read If no width is specified the command defaults to reading word sized data Example To continually rea...

Page 50: ...al width specifies the size of the access to memory The default access size is a word Examples To continually write the longword data 0x12345678 to address 0x20000 the command is lw l 20000 12345678 N...

Page 51: ...ending address is provided then MD will display memory up to an address that is 128 beyond the starting address This command first aligns the starting address for the data access size and then increme...

Page 52: ...a If no value for data is provided then the MM command enters into a loop The loop obtains a value for data sets the contents of the current address to data increments the address according to the dat...

Page 53: ...tput from this command Type Start End Port Size SDRAM 0x00000000 0x00FFFFFF 32 bit Vector Table 0x00000000 0x000003FF 32 bit USER SPACE 0x00020000 0x00FFFFFF 32 bit MBAR 0x10000000 0x100003FF 32 bit I...

Page 54: ...ter set in a buffer The RD command displays register values from the register buffer Examples To display all the registers and their values the command is rd To display only the program counter rd pc...

Page 55: ...converted according to the user defined radix normally hexadecimal dBUG preserves the registers by storing a copy of the register set in a buffer The RM command updates the copy of the register in th...

Page 56: ...ial power on states The RESET command executes the same sequence of code that occurs at power on If the RESET command fails to reset the board adequately cycle the power or press the reset button Exam...

Page 57: ...of the machine which contains files accessible via TFTP Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist gateway...

Page 58: ...and values Examples To display all options and settings the command is show To display the current baud rate of the board the command is show baud Here is an example of the output from a show command...

Page 59: ...nt program counter and then executes the target code The STEP command can be used to step over BSR and JSR instructions The STEP command will work for other instructions as well but note that if the S...

Page 60: ...and the s option displays usage information for the symbol table Symbol names contained in the symbol table are truncated to 31 characters Any symbol table lookups either by the SYMBOL command or by...

Page 61: ...ecimal number The TRACE command sets bits in the processors supervisor registers to achieve single instruction execution and the target code executed Control returns to dBUG after a single instruction...

Page 62: ...he M5407C3 dBUG are available the updated image is downloaded to address 0x00020000 The new image is placed into Flash using the UPDBUG command The user is prompted for verification before performing...

Page 63: ...bytes to copy into the user portion of Flash If the bytes parameter is omitted then this command writes to the entire user space There are seven sectors of 256K each available as user space Users acce...

Page 64: ...ion number is separated by a decimal for example v 2b 1c 1a The version date is the day and time at which the entire dBUG monitor was compiled and built Examples To display the version of the dBUG mon...

Page 65: ...is in lower 8 bits of D1 to terminal Assembly example assume d1 contains the character move l 0013 d0 Selects the function TRAP 15 The character in d1 is sent to terminal C example void board_out_char...

Page 66: ...esent A non zero value in D0 means a character is present Assembly example move l 0014 d0 Select the function trap 15 Make the call d0 contains the response yes no C example int board_char_present voi...

Page 67: ...Chapter 2 Using the Monitor Debug Firmware 2 41 TRAP 15 Functions asm trap 15 exit and transfer to dBUG Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 68: ...2 42 M5407C3 User s Manual TRAP 15 Functions Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 69: ...two Timers 4 KBytes of SRAM Freescale M Bus Module supporting the I 2 C two byte wide parallel I O port and the supporting integrated system logic All the registers of the core processor are 32 bits w...

Page 70: ...ignal is available on the 120 pin expansion connector J1 This signal should not be driven by the user 3 1 4 Clock Circuitry The M5407C3 uses a 50MHZ oscillator U21 to provide the clock to CLKIN pin of...

Page 71: ...0 to 3 will be assigned However the software watchdog is programmed for Level 7 priority 2 and uninitialized vector The UART0 is programmed for Level 3 priority 2 and autovector The UART1 is programme...

Page 72: ...gisters are programmed by dBUG to map the external memory and I O devices The M5407C3 uses chip select zero CS0 to enable the Flash ROM refer to Section 3 3 The M5407C3 uses RAS1 RAS2 CAS0 CAS1 CAS2 a...

Page 73: ...processor starts a bus cycle by asserting TS with other control signals The processor then waits for an acknowledgment TA either from within Auto acknowledge mode or by the externally addressed device...

Page 74: ...en using double sided DIMMs only half of the available memory will be accessible Since DIMMs are manufactured primarily for use in PCs some DIMMs have the DQM byte enables and RAS bank selects routed...

Page 75: ...code was to be placed at the base of the flash but setup so that it will download to the SDRAM starting at address 0xE0000 The user should refer to the compiler for this since it will depend upon the...

Page 76: ...tor driven from an external crystal The first 8 bytes of RAM are used to provide the clock calendar storage which are configured in BCD format The remaining 56 bytes of RAM is available for use as bat...

Page 77: ...define the registers For more information on the Davicom DM9008 visit the Davicom website www davicom8 com typedef struct NATURAL16CR union struct Even registers NATURAL16 CLDA1 CLDA1 rd PSTOP wr NATU...

Page 78: ...NATURAL16 DCR Data Configuration Register rd NATURAL16 reserved 0x10000 0x0010 2 Odd registers NATURAL16 PSTART PSTART rd CLDA0 wr NATURAL16 RNPP Remote Next Packet Pointer NATURAL16 LNPP Local Next P...

Page 79: ...D21 64 A16 5 D0 6 HIZ 65 D22 66 GND 7 D1 8 BKPT_TMS 67 GND 68 A17 9 GND 10 DSDI_TDI 69 D23 70 A18 11 D2 12 1 8V 71 D24 72 A19 13 D3 14 DSDO_TDO 73 D25 74 3 3V 15 3 3V 16 TCK 75 3 3V 76 A20 17 D4 18 D...

Page 80: ..._CAS0 DQM 0 70 1 8V 11 1 8V 12 PP2 71 R_CAS1 DQM 1 72 CLKIN 13 CS5 14 PP3 73 R_CAS2 DQM 2 74 GND 15 CS6 16 PP4 75 3 3V 76 RSTO 17 CS7 18 GND 77 R_CAS3 DQM 3 78 1 8V 19 GND 20 PP5 79 RDRAMW 80 BCLKO 21...

Page 81: ...connector J5 Figure 3 1 shows the J5 Connector pin assignment shows the pin assignment 41 IRQ1 42 PSTDDATA2 101 SCL 102 RTS1 43 1 8V 44 GND 103 SDA 104 CTS1 45 BR 46 PSTDDATA1 105 GND 106 1 8V 47 BD...

Page 82: ...2 4 6 8 10 12 14 16 18 20 22 24 26 BKPT DSCLK DEVELOPER RESERVED DSI DSO PSTDDATA7 PSTDDATA5 PSTDDATA3 PSTDDATA1 GND FREESCALE RESERVED PST_CLK TA GND GND RST_IN GND PSTDDATA6 PSTDDATA4 PSTDDATA2 PSTD...

Page 83: ...tocol need 3 network specific parameters These parameters are Internet Protocol IP address for the computer client IP IP address of the Gateway for non local traffic gateway IP and Network netmask for...

Page 84: ...a particular sub directory This is a security feature which prevents reading of arbitrary files by unknown persons For example SunOS uses the directory tftp_boot as the default TFTP directory When spe...

Page 85: ...BUG network download to fail and probably other severe network problems Make certain the client IP address is unique for the board Check for proper insertion or connection of the network cable IS stat...

Page 86: ...A 4 M5407C3 User s Manual Troubleshooting Network Problems Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 87: ...le ethernet for the 5407 Coldfire processor as well as reset It was targeted to Lattice ispLSI LV 2032 PLD CS B25D Declaration Section constants C P X Z H L C P X Z 1 0 DLYIOCHRDY0 node ISTYPE reg_d b...

Page 88: ...he ColdFire DIV6Q2 pin 17 ISTYPE reg_d buffer BALE pin 18 Output address latch enable A0 pin 19 OUTPUT A0 sent to the ethernet CS1_L pin 20 Input Chip select 1 from ColdFire CS2_L pin 21 Input Chip se...

Page 89: ...Z0 pin 43 BDM_RST_L pin 44 Input BDM reset input Lattice attributes pLSI property CLK XCLK0 CLK0 pLSI property CLK CLK8MHZ SLOWCLK pLSI property ISP ON pLSI property PULLUP ON pLSI property Y1_AS_RESE...

Page 90: ...OR OB21 IOWL IOW OB21 RST_L RST_H IRQ3 ETHER_IRQ DB_CS_L RST_H CS3_L CS_FPCIBD_L RST_H CS0_L CS1_L CS2_L NOT_A31 A31 GNTPCI_L REQPCI_L GNTANC_L Grant PCI bus if not in use by the PCI controller GNTANC...

Page 91: ...clk XCLK0 CLK8MHZ CLK8MHZ CLK16MHZ CLK8MHZ CLK16MHZ CLK8MHZ clk XCLK0 CLK4MHZ CLK4MHZ CLK16MHZ CLK8MHZ CLK4MHZ clk XCLK0 Total div 6 to produce 8 333MHz for Ethernet controller Davicom DM9008 from 50...

Page 92: ...A clk XCLK0 STARTISA CS3_L ENDIT STARTISA clk CLK8MHZ CBU43 BCLK0 BCLK1 BCLK2 CLK8MHZ STARTISA STARTISA BALE STARTISA CLK8MHZ BCLK2 BCLK1 BCLK0 IOR IOW IOR STARTISA BCLK2 BCLK1 BCLK0 CLK8MHZ RD IOR CS...

Page 93: ...OCHRDY0 clk CLK8MHZ DLYIOCHRDY IOCHRDY CLK8MHZ DLYIOCHRDY CLK8MHZ Test Vector Section test_vectors HIZ_L Test Vector XCLK0 PORIN_L BDM_RST_L CS3_L RST_H P 1 1 1 X C 1 1 1 X C 1 0 1 X C 1 0 1 X C 1 1 1...

Page 94: ...B 8 M5407C3 User s Manual C 0 1 1 X C 0 1 1 X C 1 1 1 X C 1 1 1 X C 1 1 1 X C 1 1 1 X C 1 1 0 X C 1 1 1 X C 1 1 1 X C 1 1 1 X end Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 95: ...5307mux device ispLSI22LV10 This abel file contains the code to mux the address lines allowing the MCF5407 to support all 168pin 1Bank x 64 bit PC compliant DIMMS It was targeted to Lattice ispLSI 22L...

Page 96: ...t address A10 SA11 PIN 17 Output SDRAM input address A11 SA12 PIN 27 Output SDRAM input address A12 SA13 PIN 20 Output SDRAM input address A13 BA0 PIN 18 Output SDRAM input address BA0 BA1 PIN 26 Outp...

Page 97: ...1 BA0 CA22 BA1 CA23 when select 2 then SA8 CA19 SA9 CA21 SA10 CA22 BA0 CA23 BA1 CA24 when select 3 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 BA0 CA22 BA1 CA23 when select 4 then SA8 CA19 SA9 CA20 SA1...

Page 98: ...10 CA23 SA11 CA24 BA0 CA25 BA1 CA26 when select 7 then SA8 CA18 SA9 CA19 SA10 CA20 SA11 CA21 SA12 CA22 BA0 CA23 BA1 CA24 when select 8 then SA8 CA19 SA9 CA20 SA10 CA21 SA11 CA22 SA12 CA23 BA0 CA24 BA1...

Page 99: ...10 SA11 SA12 BA0 BA1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 0 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 0 1 1 1 0 1 0 1 0 1 0 1 0 X X X X X X X 0 1 0 0 1 0...

Page 100: ...C 6 BookTitle Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 101: ...C19 C20 C21 C22 C23 C24 C45 C46 C47 C48 C49 C50 C51 C53 C54 C5 5 C56 C57 C58 C59 C60 C61 C 68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C84 C85 C87 C91 C92 C93 C111 C112 C113 C11 4 C115 C116 C118 C119 C120...

Page 102: ...Ethernet controller supply filter 27 2 L3 L4 SIEMENS B82111 B C24 25uH PSU switching inductors 28 1 P1 RJ45 thru board connector 29 1 P3 Augat 25V 02 PSU bare wire connector 30 2 P5 P4 RS232 port thr...

Page 103: ...53 5 U2 U3 U4 U5 U7 MC74LCX16245DT 16 bit wide bus transceiver 54 1 U6 MC74LCX16244DT 16 bit wide bus buffer 55 1 U8 DM9008F Davicom 10BaseT ethernet controller 56 1 U9 AT93C46 10SC 2 7 8S1 I2C E2PRO...

Page 104: ...ered 1 Bank x 64 DIMM 8M or 16M support for up to 512M Volatile main system memory 73 1 U27 ispGAL22LV10 Lattice PAL SDRAM multiplexing SMT 74 1 U28 MC145407DW RS232 transceiver plus charge pump 75 1...

Page 105: ...Appendix E Schematics E 1 Appendix E Schematics Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 106: ...x 4 7K 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 D6 LED SMT GRN D3 LED SMT RED JP7 1 2 U5 MC74LCX16245DT 1B1 2 1B2 3 1B3 5 1B4 6 1B5 8 1B6 9 1B7 11 1B8 12 2B1 13 2B2 14 2B3 16 2B4 17 2B5 19 2B6 20 2B7 22 2B8 23...

Page 107: ...3 100 XTIP PP7 198 NC 179 IRQ5 70 CS1 51 IRQ7 68 GND1 4 CS2 54 IVCC1 1 CS3 55 GND2 10 CS4 56 A0 2 CS5 58 GND3 17 CS6 59 EVCC2 7 CS7 60 GND4 25 D0 147 GND5 33 EVCC3 13 GND6 41 A1 3 GND7 48 EVCC4 21 GND...

Page 108: ...0 IRQ12 92 PA4 59 IRQ15 91 SA0 96 PA3 60 MSD5_BNCSW 69 PA2 61 IOR 19 PA1 62 MSD4 68 PA0 63 SD0 26 MSD3 67 IOW 21 MSD2_EECK 66 SA1 97 MSD1_EED0 65 SMEMR 23 MSD0_EED1 64 SD1 27 RST 35 SA2 98 AEN 24 SD2...

Page 109: ...9 99 100 100 101 101 102 102 103 103 104 104 105 105 106 106 107 107 108 108 109 109 110 110 111 111 112 112 113 113 114 114 115 115 116 116 117 117 118 118 119 119 120 120 C60 1nF J2 AMP 177983 5 120...

Page 110: ...43 NC1 14 NC7 64 VDD1 4 NC8 66 NC2 16 GND1 5 NC3 38 VDD2 11 NC4 39 GND2 10 NC5 42 VDD3 15 SA0 37 VDD4 20 GND3 17 VDD5 27 GND4 21 VDD6 41 SA1 36 VDD7 54 GND5 26 VDD8 61 GND6 40 VDD9 65 QA8 63 VDD10 70...

Page 111: ...88 AD 3 89 AD 2 90 AD 1 91 AD 0 92 VSS4 93 VDD3 94 DQ 0 95 DQ 1 96 DQ 2 97 DQ 3 98 DQ 4 99 DQ 5 100 DQ 6 101 VSS5 102 VDD4 103 DQ 7 104 DQ 8 105 DQ 9 106 DQ 10 107 DQ 11 108 DQ 12 109 DQ 13 110 VSS6...

Page 112: ...I O21 42 I O10 27 I O20 41 I O11 28 I O19 40 I O12 29 I O18 39 I O13 30 I O17 38 I O14 31 I O16 37 I O15 32 TDO IN1 24 TDI IN 0 14 ispEN NC 13 TMS NC 36 TCK Y2 33 Y0 11 RESET Y1 35 GOE0 2 VCC0 12 VCC...

Page 113: ...A5 PSTDDATA7 PSTDDATA1 BCLK_SDRAM1 BCLK_SDRAM0 BCLK_SDRAM2 BCLK_SDRAM3 PSTDDATA6 PSTDDATA4 3 3 3 3 1 8 3 3 1 8 IVCC 5 3 3 3 3 5 3 3 1 8 3 3 1 8 1 8 3 3 1 8 3 3 12 12 JP12 1 2 RP32 4x 22 1 1 2 2 3 3 4...

Page 114: ...eet 5 5 VBAT VBAT 3 3 5 Y1 32 768KHz P5 5 9 4 8 3 7 2 6 1 U14 M41T11M OSCI 1 OSCO 2 VBAT 3 VSS 4 SDA 5 SCL 6 FT OUT 7 VCC 8 U29 MC145406DW DI1 14 TX1 3 DO1 15 DI2 12 RX1 2 DO2 13 DI3 10 TX2 5 DO3 11 V...

Page 115: ...DD12 110 D8 11 VDD13 124 DQM1 29 VDD14 133 A3 118 VDD15 143 DQM0 28 VDD16 157 D62 160 VDD17 168 A4 35 D7 10 A5 119 D61 159 A6 36 D6 9 A7 120 D60 158 A8 37 D5 8 A9 121 D59 156 A10_AP 38 D4 7 BA0 122 D5...

Page 116: ...12 M5407C3 User s Manual Freescale Semiconductor I Freescale Semiconductor Inc nc...

Page 117: ...n table are wrong Table 1 4 lists the correct functions 2 The descriptions of the JP16 functionality on the back of the silkscreen are wrong Table 1 2 lists the correct functions 3 The pin numbering f...

Page 118: ...emiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application...

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