3-4
M5407C3 User’s Manual
The Processor and Support Logic
configured as data space but is not used by dBUG except during system initialization. After
system initialization is complete it is available to the user. The memory is relocatable to
any 2 KByte boundary.
If one or both of the internal SRAMs will be used to store instructions, then the RAMBAR
should initially be set up for data. While the SRAM is programmed as data the code can be
loaded into the SRAM. After the code has been moved reprogram the RAMBAR so that the
SRAM is defined as instruction. Now the code stored in the SRAM can execute.
3.1.8 The MCF5407 Registers and Memory Map
The memory and I/O resources of the M5407C3 are divided into three groups, MCF5407
Internal, External resources, and the ethernet controller. All the I/O registers are memory
mapped.
The MCF5407 has built in logic and up to eight chip-select pins (-CS0 to -CS7) which are
used to enable external memory and I/O devices. In addition there are two -RAS lines for
DRAM’s. There are registers to specify the address range, type of access, and the method
of -TA generation for each chip-select and -RAS pins. These registers are programmed by
dBUG to map the external memory and I/O devices.
The M5407C3 uses chip-select zero (-CS0) to enable the Flash ROM (refer to Section 3.3.)
The M5407C3 uses -RAS1, -RAS2, -CAS0, -CAS1, -CAS2, and -CAS3 to enable the
SDRAM DIMM module (refer to Section 3.2), -CS2 for SRAM (not populated), -CS3 for
Ethernet Bus I/O space, and -CS1 for the PCI bridge chip.
The chip select mechanism of the MCF5407 allows the memory mapping to be defined
based on the memory space desired (User/Supervisor, Program/Data spaces).
All the MCF5407 internal registers, configuration registers, parallel I/O port registers,
UART registers and system control registers are mapped by MBAR register at any 1 KByte
boundary. It is mapped to 0x10000000 by dBUG. For complete map of these registers refer
to the MCF5407 User's Manual.
The M5407C3 board can have up to 512 MBytes of SDRAM installed. The first 16 MBytes
of memory space are reserved for this memory. Refer to Section 3.2 for a discussion of
RAM. The dBUG is programmed in one Am29PL160C-XX Flash ROM which occupies 2
MBytes of the address space. The first 256 KBytes are used by ROM Monitor and the
remainder is left for user use. Refer to section 3.3.
dBUG maps all the I/O space of the Ethernet bus to the MCF5407 memory at address
$40000000. Refer to section 3.6
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