3-2
M5407C3 User’s Manual
The Processor and Support Logic
U19 is used to produce active low power-on RESET signal which feeds into the
ispLSI2032. The reset switch is fed into U19 which generates U18's input for reset. The
U18 device generates the system reset (-CF_RSTI) and Ethernet RESET (ETH_RST)
signals.
dBUG performs the following configurations of internal resources during the initialization.
The instruction cache is invalidated and disabled. The Vector Base Register, VBR, points
to the Flash. A copy of the exception table is made at address $00000000 in the SDRAM.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are
placed in a stop condition. Interrupt controller registers are initialized with unique interrupt
level/priority pairs. PP[7:0] are configured as paralell port output pins and PP[15:8] are
configured as A[31:24]. PP[7:4] are general purpose outputs and PP[3:0] are used by the
ROM monitor to automaticaly configure the SDRAM address lines via the U27 mux.
3.1.3 HIZ Signal
The assertion of the -HIZ signal forces all output drivers to a high-impedance state. The
-HIZ signal is actively driven by the ispLSI2032V-100LJ (U18). -HIZ is only driven low
(asserted) during reset. This Signal is available on the 120 pin expansion connector J1. This
signal should not be driven by the user.
3.1.4 Clock Circuitry
The M5407C3 uses a 50MHZ oscillator (U21) to provide the clock to CLKIN pin of the
processor. In addition to U21, there also exist a 20MHz oscillator (U10) which feeds into
the Ethernet chip, a PCI bus master 33MHZ oscillator (U30) and a 32.768 KHZ crystal
(Y1) for the real-time clock. The CLKIN drives the clock buffer chip (U24). The buffered
CLKIN drives the 5407 and the ispLSI2032 for Ethernet timing (1/6 bus clock), SRAM
(U13), and SDRAM (U26).
3.1.5 Watchdog Timer
The duration of the Watchdog is selected by BMT0-1 bits in System Protection Register.
The dBUG initializes this register with the value 00, which provides for 1024 system clock
time-out but dBUG does NOT enable it.
3.1.6 Interrupt Sources
The ColdFire® family of processors can receive interrupts for seven levels of interrupt
priorities. When the processor receives an interrupt which has higher priority than the
current interrupt mask (in status register), it will perform an interrupt acknowledge cycle at
the end of the current instruction cycle. This interrupt acknowledge cycle indicates to the
source of the interrupt that the request is being acknowledged and the device should provide
the proper vector number to indicate where the service routine for this interrupt level is
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