Freescale Semiconductor M5407C3, User Manual

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vi M5407C3 User’s Manual
CONTENTS
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Number
Title
Page
Number
2.5 TRAP #15 Functions ........................................................................................ 2-39
2.5.1 OUT_CHAR ................................................................................................. 2-39
2.5.2 IN_CHAR ..................................................................................................... 2-39
2.5.3 CHAR_PRESENT ........................................................................................ 2-40
2.5.4 EXIT_TO_dBUG.......................................................................................... 2-40
Chapter 3
Hardware Description and Reconfiguration
3.1 The Processor and Support Logic ....................................................................... 3-1
3.1.1 Processor ......................................................................................................... 3-1
3.1.2 Reset Logic ..................................................................................................... 3-1
3.1.3 HIZ Signal....................................................................................................... 3-2
3.1.4 Clock Circuitry ............................................................................................... 3-2
3.1.5 Watchdog Timer ............................................................................................. 3-2
3.1.6 Interrupt Sources............................................................................................. 3-2
3.1.7 Internal SRAM................................................................................................ 3-3
3.1.8 The MCF5407 Registers and Memory Map ................................................... 3-4
3.1.9 Reset Vector Mapping .................................................................................... 3-5
3.1.10 TA Generation ................................................................................................ 3-5
3.1.11 Wait State Generator....................................................................................... 3-6
3.1.12 SDRAM DIMM .............................................................................................. 3-6
3.1.13 Flash ROM...................................................................................................... 3-7
3.1.14 JP15 Jumper and User’s Program ................................................................... 3-7
3.2 Serial Communication Channels......................................................................... 3-7
3.2.1 MCF5407 UARTs........................................................................................... 3-7
3.2.2 I2C Module ..................................................................................................... 3-8
3.3 Real-Time Clock................................................................................................. 3-8
3.4 Parallel I/O Port .................................................................................................. 3-8
3.5 On-Board Ethernet Logic.................................................................................... 3-8
3.6 Connectors and Expansion Bus ........................................................................ 3-11
3.6.1 Expansion Connectors - J1 and J2 ................................................................ 3-11
3.6.2 The Debug Connector J5 .............................................................................. 3-13
Appendix A
Configuring dBUG for Network Downloads
Appendix B
ColdFire to ISA, IRQ7 and Reset Logic Abel Code
Appendix C
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