Chapter 3. Hardware Description and Reconfiguration
3-1
Chapter 3
Hardware Description and
Reconfiguration
This chapter provides a functional description of the M5407C3 board hardware. With the
description given here and the schematic diagram in Appendix E, the user can gain a good
understanding of the board's design. In this manual, an active low signal is indicated by a
"-" preceding the signal name in this text and a bar over the signal name in the schematics.
3.1 The Processor and Support Logic
This part of the Chapter discusses the CPU and general supporting logic on the M5407C3
board.
3.1.1 Processor
The microprocessor used in the M5407C3 is the highly integrated
Freescale
ColdFire® MCF5407,
32-bit processor. The MCF5407 implements a ColdFire version 4 core with 16 KByte instruction
cache and 8 KByte of data cache, two UART channels, two Timers, 4 KBytes of SRAM,
Freescale
M-Bus Module supporting the I
2
C, two-byte wide parallel I/O port, and the supporting integrated
system logic. All the registers of the core processor are 32 bits wide except for the Status Register
(SR) which is 16 bits wide. This processor communicates with external devices over a 32-bit wide
data bus, D0-D31 with support for 8 and 16-bit ports. This chip can address 4 GBytes of memory
space using internal chip-select logic. All the processor's signals are available through the
expansion connectors (J1 and J2). Refer to section 3.6 for pin assignment.
The MCF5407 has an IEEE JTAG-compatible port and BDM port used with third party
tools. The board is configured to boot up in the normal/BDM mode of operation. These
signals are available at port J5. The processor also has the logic to generate up to eight (8)
chip selects, -CS0 to -CS7, and support for 2 banks of ADRAM (not on evaluation board)
or 2 banks of SDRAM (on evaluation board).
3.1.2 Reset Logic
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