Freescale Semiconductor ColdFire MCF5274, User Manual

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1-14 M5275EVB User’s Manual
Communication Ports
— 10-Mbps IEEE 802.3 MII
— 10-Mbps 7-wire interface (industry standard)
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Support for full-duplex operation (200Mbps throughput) with a minimum system
clock rate of 50MHz
• Support for half-duplex operation (100Mbps throughput) with a minimum system
clock rate of 25 MHz
• Retransmission from transmit FIFO following a collision (no processor bus
utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and
address recognition rejects (no processor bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
For more details see the MCF5275 Reference manual. The on board ROM Monitor is
programmed to allow a user to download files from a network to memory in different
formats. The current compiler formats supported are S-Record, COFF, ELF or Image.
1.4.3 BDM/JTAG Port
The MCF5275 processor has a Background Debug Mode (BDM) port, which supports
Real-Time Trace and Real-Time Debug. The signals which are necessary for debug are
available at connector (J1). Figure 1-4 shows the (J1) Connector pin assignment.