Freescale Semiconductor ColdFire MCF5274, User Manual, Page: 17 / 104

Chapter 1. M5275EVB Introduction 1-9
Support Logic
1.3 Support Logic
1.3.1 Reset Logic
Reset occurs during power-on or via assertion of the signal RESET which causes the
MCF5275 to reset. RESET is triggered by the reset switch (SW5) which resets the entire
processor/system.
The dBUG Firmware configures the MCF5275 microprocessor internal resources during
initialization. The contents of the exception vector table are copied to address 0x0000_0000
in the SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and
the internal timers are placed in a stop condition. A memory map for the entire board can
be seen in Table 1-2.
If the external RCON pin is asserted (SW6-1 ON) during reset, then various chip functions,
including the reset configuration pin functions after reset, are configured according to the
levels driven onto the external data pins. See tables below on settings for reset
configurations.
If the RCON pin is negated (SW6-1 OFF) during reset, the chip configuration and the reset
configuration pin functions after reset are determined by the RCON register or fixed
defaults, regardless of the states of the external data pins.
Table 1-4. SW6-1 RCON
SW6-1 Reset Configuration
OFF RCON not asserted, Default Chip configuration or RCON register settings
ON RCON is asserted, Chip functions, including the reset configuration after reset,
are configured according to the levels driven onto the external data pins.
Table 1-5. SW6-2 JTAG_EN
SW6-2 JTAG Enable
OFF JTAG interface enabled
ON BDM interface enabled
Table 1-6. SW6-[4:3] Encoded Clock Mode
SW6-3 SW6-4 Clock Mode
ON ON Normal PLL mode with external clock reference
ON OFF Normal PLL mode with external clock reference
OFF ON External clock mode- (PLL disabled)
OFF OFF 1:1 PLL mode