Freescale Semiconductor ColdFire MCF5274, User Manual

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1-20 M5275EVB User’s Manual
Connectors and User Components
1.5.2 Reset Switch (SW5)
The reset logic provides system initilization. Reset occurs during power-on or via assertion
of the signal RESET which causes the MCF5275 to perform a hardware reset. Reset is also
triggered by the reset switch (SW5) which resets the entire processor/system.
A hard reset and voltage sense controller (U20) is used to produce an active low power-on
RESET signal. The reset switch SW5 is fed into U18 which generates the signal which is
fed to the MCF5275 reset, RESET. There are three sources of reset on the board:
1. Power sense and reset switch circuit (U20 and SW5)
2. BDM reset from J1
3. External reset for the expansion connector (J5)
15 CS0 16 SD_CLKOUT
17 SD_A10 18 TIP
19 SD_CLKOUT 20 R/W
21 CS1 22 TEA
23 RTS2 24 RCON
25 RXD2 26 TXD2
27 CTS2 28 GND
29 GND 30 PST3
31 PST2 32 PST1
33 PST0 34 GND
35 GND 36 DDATA3
37 DDATA2 38 DDATA1
39 DDATA0 40 GND
41 GND 42 QSDO
43 CLKOUT 44 GND
45 GND 46 PCS0
47 PSC2 48 PSC3
49 PSC1 50 GND
51 GND 52 QSDI
53 CLKMOD0 54 CLKMOD1
55 JTAG_EN 56 SCK
57 GND 58 GND
59 GND 60 GND
Table 1-15. J6 Pinout
(Continued)
Pin Signal Pin Signal