Fortec Star CM1-BT1, Manual

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70 Using the Module
4.7 Memory Address Map
There are 64 GB (36-bits) of physical address space that can be used as:

Memory Mapped IO (MMIO - IO fabric)
 Physical Memory (DRAM)
The CPU core can access the full physical address space, while downstream devices can only
access SoC DRAM, and each CPU core’s local APIC. Peer to peer transactions are not sup-
ported.
Most devices map their registers and memory to physical address space. This chapter summa-
rizes the possible mappings.
The SoC supports four different address spaces:
 Physical Address Space

IO Address Space
 PCI Configuration Space

Message Bus Space
The SoC Transaction Router maps the physical address space as follows:

CPU core to DRAM
 CPU core to IO fabric (MMIO)

CPU core to extended PCI registers (ECAM accesses)
 IO fabric to CPU cores (local APIC interrupts)
The CPU core can only directly access memory space through memory reads and writes and IO
space through the IN and OUT IO port instructions. PCI configuration space is indirectly
accessed through IO or memory space, and the Message Bus space is accessed through PCI
configuration space.
Although 64 GB (36-bits) of physical address space is accessible, some MMIO must exist for
devices and software with 32-bit limits. Further, all DRAM should remain accessible for devices
and software with access to memory above 4 GB. These goals are accomplished by moving a
section DRAM to start at the fixed 4 GB boundary, leaving a hole below 4 GB for MMIO. This
creates the following distinct memory regions:

DOS DRAM + Low DRAM
 Low MMIO

High DRAM
 High MMIO
There are two registers used to create these regions, BMBOUND and BMBOUND_HI.