M
ODEL
SDP100 V
ERSION
V_1.00
P
REPARED BY
H/W
D
ATE
25/05/2007
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
48/70
Figure 38. Reset Scheme used in MT6228
- Hardware Reset
This Reset is inputted through the SYSRST# pin from PMIC(MT6305BN Pin 24). The SYSRST# shall be driven to
low during power-on. The Hardware reset has a global effect on the chip. It initializes all digital and analog circuits
except the RTC. Refer to the listed below.
-
All Analog Circuits are turned off
-
All PLLs are turned off and bypassed. The 13Mhz system clock is the default time base.
-
Special Trap statue in GPIO.
- Watchdog Reset
A Watchdog reset is generated when the Watchdog timer expires as the MCU software failed to re-program the
timer counter in time. Hardware blocks that are affected by the watchdog reset are :
- MCU Subsystem
- DSP Subsystem
- External Component (By software program)
- Software Reset
These are local reset signals that initialize specific hardware. For example, The MCU or DSP software may write to
software reset trigger registers to reset hardware modules to their initial states, when hardware failures are detected.
The following Modules has software resets
-
DSP Core
-
DSP Coprocessors.
SDP100
T
ECHNICAL
M
ANUAL
Page 3.48