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M

ODEL

 

            

SDP100 V

ERSION

 V_1.00 

P

REPARED BY

 H/W 

D

ATE

 25/05/2007 

S

UBJECT

 

T

ECHNICAL 

M

ANUAL

 

P

AGE

 43/70 

 

 6.2 Blue Tooth Stage 

Also, MT6228 has a Digital Audio Interface(DAI) block to communicate with the System Simulator for FTA or external 

Bluetooth module for particular applications. The digital filter block performs filter operations for voice band and audio band 

signal processing. 

 

 

Figure 33. The digital circuits for Audio Front-End 

 The Below table is shown the MT6228 DAI/PCM Port mapping according to S/W concept. 

 

 The BT Module is used CS224 from Delta and BTVZ0502SA from Samsung. The BT Version is 1.2 and Nominal Power is 

0dBm and Sensitivity is about -80dBm. The distance during communication for Voice and Audio is around 13meter. 

BT Chip is BlueCore 3.So, If BT headset has a CSR Chip set, The paring is no problem. The BT Test is certificated in BQB. 

 

 

 

SDP100

 

T

ECHNICAL 

M

ANUAL                                                                                                                                 

Page 3.43

 

Summary of Contents for SDP100

Page 1: ...28 GSM GPRS Baseband Processor 1 System OverView The Revolutionary MT6228 is a leading edge single Chip solution for GSM GPRS mobile phones targeting the emerging applications in digital audio and vid...

Page 2: ...r Division coprocessor PPP Framer coprocessor z External Memory Interface Supports up to 4 external devices Supports 8 bit or 16 bit memory components with maximum size of up to 64M bytes each Support...

Page 3: ...igital and analog loop back modes for both Audio and baseband front end DAI port complying with GSM Rec 11 10 JTAG port for debugging embedded MCU 1 2 Model Feature z Radio Interface and Baseband Fron...

Page 4: ...tion Compliant with GSM 03 50 1 3 Multimedia Feature z LCD NAND Flash Interface Dedicated Parallel Interface supports 3 external devices with 8 16 bits NAND flash interface 8 9 16 18 bit Parallel inte...

Page 5: ...EC 10918 2 compliance Supports YUV422 and YUV420 and grayscale formats Supports JFIF Standard DC and AC Huffman tables Provides 4 levels of encode quality Supports continuous shooting z Image Data Pro...

Page 6: ...ed MV Reverible VLC Short Header Supports encoding motion vector of range up to 64 63 5 pixels HE AAC decode support AAC AMR WB AMR audio decode support AMR WB AMR audio encode support z TV OUT Suppor...

Page 7: ...V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 7 70 Figure 2 is shown the Block Diagram of MT6228 for detailly Figure 2 Block Diagram of MT6228 2 Product Description SDP100 TECHN...

Page 8: ...ECHNICAL MANUAL PAGE 8 70 Pin Outs One type of Package for this product TFBGA 13x13mm 296balls 0 65mm pitch package is offered Pin outs and the top view are illustrated in Figure 3 4 Pin Out Figure 3...

Page 9: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 9 70 Top Masking Definition Figure 5 Top masking definition SDP100 TECHNICAL MANUAL Page 3 9...

Page 10: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 10 70 Pin Description SDP100 TECHNICAL MANUAL Page 3 10...

Page 11: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 11 70 SDP100 TECHNICAL MANUAL Page 3 11...

Page 12: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 12 70 SDP100 TECHNICAL MANUAL Page 3 12...

Page 13: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 13 70 SDP100 TECHNICAL MANUAL Page 3 13...

Page 14: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 14 70 SDP100 TECHNICAL MANUAL Page 3 14...

Page 15: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 15 70 SDP100 TECHNICAL MANUAL Page 3 15...

Page 16: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 16 70 SDP100 TECHNICAL MANUAL Page 3 16...

Page 17: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 17 70 SDP100 TECHNICAL MANUAL Page 3 17...

Page 18: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 18 70 SDP100 TECHNICAL MANUAL Page 3 18...

Page 19: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 19 70 SDP100 TECHNICAL MANUAL Page 3 19...

Page 20: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 20 70 SDP100 TECHNICAL MANUAL Page 3 20...

Page 21: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 21 70 SDP100 TECHNICAL MANUAL Page 3 21...

Page 22: ...ip This is accomplished by request grant handshaking protocol between masters and arbiters Figure 6 Block Diagram of MCU in MT6228 3 1 Processor Core The Micro Controller Unit subsystem in MT6228 uses...

Page 23: ...onfigurations for different applications are needed Factory Programming The configuration for factory programming is shown in Figure 8 Usually the Factory Programming Host connects with MT6228 via the...

Page 24: ...ull up resistor for RXD 3 3 Interrupt Controller Figure 10 outlines the major functionality of the MCU Interrupt Controller The interrupt controller processes all interrupt sources coming from externa...

Page 25: ...errupt controller that can support up to 4 interrupt requests coming from external sources the EINT0 3 and 4 wake up interrupt requests The four external interrupts can be used for different kind of a...

Page 26: ...erface connected to a system backbone AHB The module operates on the same clock as the AHB and has a 32 bit wide organization 3 5 External Memory Interface MT6228 incorporates a powerful and flexible...

Page 27: ...pulse sequences with programmable frequency and duty cycle for LCD backlight or charging purpose The duration of the PWM output signal is low as long as the internal counter value is greater than or...

Page 28: ...umns and 6 rows The other is the key detection block which provides key pressed key released and de bounce mechanism Each time the key is pressed or released i e something different in the 7x6 matrix...

Page 29: ...setting the control registers MCU software can control the direction the output value and read the input values on these pins These GPIOs and GPOs are multiplexed with other functionalities to reduce...

Page 30: ...LD12 NLD13 NLD14 NLD15 NLD16 NLD17 NAND FLASH and Parallel LCD data signals MFIQ MIRQ external interrupt MCDA4 MCDA5 MCDA6 MCDA7 MMC4 0 data signals Multiplexed of Signals on GPO SRCLKENA SRCLKENAN po...

Page 31: ...ial will work as a window material Polycarbonate is recommended The surface finish of the plastic should be smooth without any texture Shape of the Window From an optics standpoint the window should b...

Page 32: ...tuned Figure 19 RTC Circuit Auxiliary ADC Unit The auxiliary ADC unit is used to monitor the status of battery and charger identify the plugged peripheral and perform temperature measurement There pr...

Page 33: ...2D graphics engine TV encoder and advanced hardware LCD display controller A lot of attractive multimedia functions can be realized through above hardware accelerators in MT6228 The functions include...

Page 34: ...odules For Parallel LCD Modules The interface pins are 6pins and 18bit data lines LWR write enable signal LRD read enable signal LPAO Register select signal To enter the command and data LST reset sig...

Page 35: ...its I O interface The NFI core can automatically generate ECC parity bits when programming or reading the device Used 7 control Signal NRE NEW NCE NALE WATCHDOG NCLE NRNB In SDP100 The Nand Flash Memo...

Page 36: ...ical Layer Specification version 1 0 as well as the MultiMediaCard MMC bus protocol as defined in MMC system specification version 2 2 Since SD Memory Card bus protocol is backward compatible to MMC b...

Page 37: ...k for master type image sensor and accept vertical horizontal synchronization signal and sensor data and then generate grabbed area of raw data or YUV422 RGB565 data to the lens sensor compensation un...

Page 38: ...image playback mode the source is in RGB565 format In this mode still images can be displayed The LCM controller can direct the image path to the TV controller When the LCM controller sends frames to...

Page 39: ...s of voice and audio data paths Figure 29 shows the block diagram of the audio front end All voice band data paths comply with the GSM 03 50 specification Mono hands free audio or external FM radio pl...

Page 40: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 40 70 Figure 29 Audio Front End Block Diagram SDP100 TECHNICAL MANUAL Page 3 40...

Page 41: ...hz These are important for FM Radio Blocking of 100Mhz and must be placed to near by Headset connector Also has a good performance for EMI Because The FM Radio Ant is connected to EJ_OUTL The ADC5_HF_...

Page 42: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 42 70 Figure 32 Audio Amp Circuit Diagram Figure 33 Mic Circuit diagram SDP100 TECHNICAL MANUAL Page 3 42...

Page 43: ...nd and audio band signal processing Figure 33 The digital circuits for Audio Front End The Below table is shown the MT6228 DAI PCM Port mapping according to S W concept The BT Module is used CS224 fro...

Page 44: ...l scheme the MT6228 radio interface consists of Baseband Serial Interface BSI Baseband Parallel Interface BPI Automatic Power Control APC and Automatic Frequency Control AFC together with APC DAC and...

Page 45: ...PA_EN PAM Enable PAM RF3166 BPI_BUS 5 BANDSW_DCS Band switch for DCS PAM RF3166 BPI_BUS 8 BT_LDO_EN Blue Tooth Power Supply Enable BTM CR222 BPI_BUS 9 RFVCOEN RF VCO Enable Transceiver MT6120 Figure 3...

Page 46: ...525 610 610 Voltage Level according to TX Power GSM Level 19 5 DCS PCS Level 15 0 profile 0 ramp up 0 0 0 0 0 0 2 4 8 26 65 143 228 255 255 255 profile 0 ramp down 255 255 239 197 138 78 32 10 0 0 0 0...

Page 47: ...ns time and date with counters In low power mode the 13Mhz time base is turned off so the 32 768Khz clock shall be employed to update the critical TDMA timer and Watchdog timer This Time base is also...

Page 48: ...hz system clock is the default time base Special Trap statue in GPIO Watchdog Reset A Watchdog reset is generated when the Watchdog timer expires as the MCU software failed to re program the timer cou...

Page 49: ...i and nickel metal hydride NiMH batteries The MT6305BNBN contains three open drain output switches for LED alerter and vibrator control The SIM interface provides the level shift between SIM card and...

Page 50: ...L MANUAL PAGE 50 70 SDP100 TECHNICAL MANUAL Page 3 50 1 Low Dropout Regulator and Reference The MT6305BNBN integrates seven LDOs that are optimized for their given functions by balancing quiescent cur...

Page 51: ...00 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 51 70 Figure 40 Functional Block Diagram of MT6305BN Figure 41 Status of Mobile Handset and LDOs SDP100 TECHNICAL MANUAL...

Page 52: ...Decoupling Capacitor C156 must be higher than X5R type 6 RTC LDO Vrtc The RTC LDO is a regulator that could source 200uA with 1 2V output voltage with Pin3 GND If Pin3 is not GND The Output Voltage i...

Page 53: ...to 7 colored indicator LED In SDP100 dedicated to Slide Key BackLight LED ALERTER pin is dedicated to Main KEY BackLight LED VIBRATOR pin is dedicated to Vibrator Motor 11 Battery Charger BATUSE pin...

Page 54: ...MEM and VCORE must be used 4 7uF 2012 type IV HYC0UEE0CF1P 512M 64Mx8bit Nand FLASH Memory and 256M 16Mx16bit Mobile SDRAM Multi Chip Package The HYC0UEE0CF1 P Series is suited for mobile communicatio...

Page 55: ...ION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 55 70 The devices are available in the following packages 149 Ball P FBGA Type 10x14 0mm 0 8mm pitch Lead Free SDP100 TECHNICAL...

Page 56: ...V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 56 70 NAND FLASH MEMORY 528MBIT 528 BYTES X 32 PAGES X 4 096 BLOCKS Figure 45 Nand Flash Block diagram and Memory Cell SDP100 TECHN...

Page 57: ...ED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 57 70 Organized as 4banks of 4 194 304x16 Figure 46 SDRAM Block diagram DC Operating Voltage DC Characteristics Nand Flash Memory VCC 2 5V 3 0V...

Page 58: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 58 70 DC Characteristics Mobile SDRAM VDD VDDQ 1 7 1 95V SDP100 TECHNICAL MANUAL Page 3 58...

Page 59: ...fractional N synthesizer with an on chip RF VCO Features Receiver Very low IF architecture Quad band differential input LNAs Quadrature RF mixers Fully integrated channel filter More than 100 dB gain...

Page 60: ...AL PAGE 60 70 Figure 47 MT6120 Functional block diagram Recommended Operating Range Item Symbol Min Typ Max Unit Power Supply Voltage VBAT VBAT 3 1 3 6 4 6 V Power Supply Voltage VCCD VCCD 2 5 2 8 3 1...

Page 61: ...DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 61 70 A description of MT612X hardware control pins and their functionality are shown in the table below MT612X has an internal VCXO and its control Pin D...

Page 62: ...s and a final low pass filter The very low IF MT6120 uses image rejection mixers and filters to eliminate interference With accurate RF quadrature signal generation and mixer matching techniques the i...

Page 63: ...format 2 Transmitter The MT6120 transmitter section consists of two on chip TX VCOs buffer amplifiers a down converting mixer a quadrature modulator an analog phase detector and a digital phase freque...

Page 64: ...synthesizer After the calibration a fast acquisition system is utilized for a period of time to facilitate fast locking The frequency ranges of the synthesizer for RX mode are RX mode GSM850 1737Mhz...

Page 65: ...in series resonance with a standard 26Mhz crystal The Crystal is connected from the Input pin XAL of Amplifier to ground through a series load capacitance The buffer provides a typical 600mVpp voltage...

Page 66: ...battery voltage thereby minimizing switching transients The RF3166 requires no external routing or external components simplifying layout and reducing board space The VRamp Range is from 0 26V to 2 1V...

Page 67: ...MODEL SDP100 VERSION V_1 00 PREPARED BY H W DATE 25 05 2007 SUBJECT TECHNICAL MANUAL PAGE 67 70 Figure 49 Power control sequence SDP100 TECHNICAL MANUAL Page 3 67...

Page 68: ...perational band The 3 rd BSI ST3 is used to command transceiver entering idle mode All bands GSM DCS PCS share the same timing BPI interface In order to simply the parallel control mechanism and achie...

Page 69: ...enna Switch Module for GSM900 DCS1800 and PCS1900 of Murata with Three SAW Modules Control Pins VC1 VC2 and VC3 are connected to LB_TX HB_TX and PCS_RX signals from baseband processor The Control Pins...

Page 70: ...he synthesizer and set its N Counter to lock the operation frequency The 2 nd BSI SR2 is used to set the receiving amplifier gain received mode and operation band of transceiver The 3 rd BSI SR3 is us...

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