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AN19E/AN19C Mainboard Manual
Precharge to Active (Trp)
This item refers to the number of cycles required to return data to its original
location to close the bank or the number of cycles required to page memory
before the next bank activate command can be issued. The default is by
DRAM SPD.
Options: 3T, 2T.
Active to Precharge (Tras)
This item specifies the number of clock cycles needed after a bank active
command before a precharge can occur (sets the minimum RAS pulse width.).
The default is by DRAM SPD.
Options: 6T, 5T.
DCLKI/DCLKO Timing
Options: 0ns, 0.5ns, 1ns, 1.5ns, Auto.
DRAM CAS Latency
Enables you to select the CAS latency time. The value is set at the factory
depending on the DRAM installed. Do not change the values in this field
unless you change specifications of the installed DRAM and DRAM clock
from DRAM Timing Selectable. The default is set by SPD (see ‘DRAM Tim-
ing’).
Options: 1.5, 2, 2.5, 3.
Bank Interleave
The item allows you to set how many banks of SDRAM support in your
mainboard. Default is by SPD.
Options: 2 Bank, 4 Bank, Disabled.
DRAM Timing
For setting DRAM Timing, By SPD is follow SDRAM Serial Presence Detect
Specification.
Options: Manual, Auto by SPD.