28
Advanced System Diagnostics and Troubleshooting Guide
Packet Errors and Packet Error Detection
Figure 8: Generalized switch block diagram
The following sections describe the hardware and software components that work together to detect
and manage packet error incidents within the Extreme Networks switch.
Hardware System Detection Mechanisms
All Extreme Networks switches based on the “
i
”-series switch fabric validate data integrity internal to
the switch fabric using a common
checksum
verification algorithm. Using
Figure 8
as a generalized
model, when a packet is received at an Ethernet network interface, the receiving MAC ASIC verifies the
Ethernet CRC: it computes a CRC value by applying the same algorithm used to compute the CRC
value appended to the received packet data by the transmitting switch. If the algorithm and the data it
is applied to are the same on both ends of the Ethernet link, the CRC values should match. If they do
not, the packet is assumed to have been damaged and is discarded.
If the CRC values match, the MAC ASIC must then transfer the packet to the internal switch fabric.
Before doing this, however, it produces a checksum value based on the packet data being passed to the
switch fabric. This checksum value becomes the
packet
checksum
. It is prepended to the packet and
both the packet checksum and packet are passed on to the switch fabric.
After the switch fabric is finished processing the packet and has made a decision regarding where the
packet is to be forwarded, it passes the packet to the transmitting MAC ASIC. The transmitting MAC
ASIC performs the reverse of the process performed by the receiving MAC ASIC. It first computes a
checksum value based on the packet data received from the switch fabric. We will call this value the
verification
checksum
.
The transmitting MAC ASIC then compares the verification checksum against the packet checksum. If
the two values do not match, the result is a
checksum
error
. The MAC ASIC maintains a count of every
checksum error that occurs on every port. When a packet is found to have a checksum error, it is still
1
PHY port and MAC device layer
4
Control bus
2
Packet bus (PBUS)
5
Packet memory
3
Forwarding ASICs
6
CPU subsystem
CG_002B
AS
I
C
AS
I
C
CPU
sub-system
DMAC
MAC
MAC
3
6
5
4
1
2
Summary of Contents for ExtremeWare Version 7.8
Page 8: ...8 Advanced System Diagnostics and Troubleshooting Guide Contents...
Page 14: ...14 Advanced System Diagnostics and Troubleshooting Guide Introduction...
Page 24: ...24 Advanced System Diagnostics and Troubleshooting Guide i Series Switch Hardware Architecture...
Page 48: ...48 Advanced System Diagnostics and Troubleshooting Guide Software Exception Handling...
Page 102: ...102 Advanced System Diagnostics and Troubleshooting Guide Additional Diagnostics Tools...
Page 110: ...110 Advanced System Diagnostics and Troubleshooting Guide Troubleshooting Guidelines...
Page 120: ...120 Advanced System Diagnostics and Troubleshooting Guide Index...