Extreme Networks ExtremeWare Version 7.8, Troubleshooting Manual

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18 Advanced System Diagnostics and Troubleshooting Guide
“i” Series Switch Hardware Architecture
BlackDiamond I/O Modules
Each BlackDiamond I/O module has a built-in switching fabric (see Figure 3 ) giving the module the
capability to switch local traffic on the same module. Traffic that is destined for other modules in the
chassis travels across the backplane to the MSMs, where it is switched and sent to its destination I/O
module.
Figure 3: BlackDiamond I/O module architecture (G8Xi 32 Gb fabric shown)
Each BlackDiamond I/O module has eight load-shared Gigabit Ethernet links to both MSMs through
the backplane. The load sharing algorithm distributes traffic across different channels through the
backplane’s Gigabit Ethernet links, providing bi-directional communication.
Each BlackDiamond I/O module is equipped with the following kinds of hardware components:
• PHY: An industry-standard ASIC responsible for physical layer (layer 1) signal, clocking, etc.
• MAC: The MAC handles the standard MAC layer functions as well as some other functions to
prepare a packet for transmission to the switch fabric or to the external network, including 802.1p
and DiffServ examination, VLAN insertion, MAC substitution, TTL decrement, 802.1p and DiffServ
replacement, etc.
Each I/O module has both external MACs and internal MACs. External MACs handle the interface to
the external ports; internal MACs handle the interface to the BlackDiamond backplane. Each MSM
provides four Gigabit Ethernet links to each I/O module.
• PBUS: The packet data bus that transfers packets between the MAC and the packet memory.
•
Switch engine (distributed packet processor) ASIC (Twister) and its associated memories: packet
RAM and FDB RAM. The SE ASIC implements a high-speed, parallel data transfer bus for
transferring packets from MACs to packet memory and back.
• Address filtering and queue management ASIC (Quake) and its associated memories: OTP RAM, PQ
RAM, and VPST RAM.
When a data packet is received by the PHY, the PHY passes the packet to the MAC. The MAC handles
the layer 2 tasks, such as tagging and the MAC address, then transfers the packet across the PBUS to the
AFQM
ASIC
OTP RAM
4x GbE to
MSM-A
4x GbE to
MSM-B
PHY
PHY
MAC
MAC
MAC
MAC
PQ RAM
VPST RAM
SRAM (Packet Mem + FDB)
DN_026C
SE
ASIC
SE
ASIC
SE
ASIC
SE
ASIC
PBUS