6
The central core of ARM Cortex-M3 processor, based on a 3-stage pipeline
Harvard bus architecture,
incorporates advanced features including single cycle
multiply and
hardware divide
to deliver an outstanding efficiency of 1.25
DMIPS/MHz. The ARM Cortex-M3 processor also implements the new Thumb®-2
instruction set architecture, which combined with features such as unaligned data
storage and atomic bit manipulation delivers 32-bit performance at a cost equivalent to
modern 8- and 16-bit devices.
Summary of Contents for EX-9132C-2
Page 1: ...Operation Manual of EX 9132C 2 DDS Serial to TCP IP Converter Version 1 1 0 25th Jan 2010 ...
Page 15: ...14 Wiring Architecture RS 232 Wiring Architecture RS 422 RS 485 Wiring Architecture ...
Page 35: ...34 Figure 6 2 Select TCP IP Winsock option at the Connect using field see Figure 6 3 ...
Page 38: ...37 Figure 6 5 ...