Detailed hardware description
Issue G
95
Colour mapping
The colour mapping of the APOLLO LVDS LCD interface is compatible with the VESA
industry standard colour mapping for LCD displays. The figure below and the table that
follows show the configuration for the colour bits in a three channel 6-bit/pixel LVDS bit
stream, and the relationship to its clock:
G0
R5
R4
R3
R2
R1
R0
B1
B0
G5
G4
G3
G2
G1
DE
VS
HS
B5
B4
B3
B2
Data for Current Clock Cycle
Previous Clock Cycle
IYA2
IYA1
IYA0
CLKA
APOLLO LVDS
Common LVDS LCD signal names
IYA0-
RxIN0-, Rin0-, D0-, Link 0-, IN0-
IYA0+
RxIN0+, Rin0+, D0+, Link 0+, IN0+
IYA1-
RxIN1-, Rin1-, D1-, Link 1-, IN1-
IYA1+
RxIN1+, Rin1+, D1+, Link 1+, IN1+
IYA2-
RxIN2-, Rin2-, D2-, Link 2-, IN2-
IYA2+
RxIN2+, Rin2+, D2+, Link 2+, IN2+
ICLKA-
CKIN-, ClkIN-, CK-, Clock-, CLK-
ICLKA+
CKIN+, ClkIN+, CK+, Clock+, CLK+
Dual channel operation
The APOLLO LVDS display interface connector supports dual channel LVDS displays.
Commonly these displays have a screen resolution greater than 1024x768. The
secondary LVDS display channel on the APOLLO board occupies the remaining
connections on the LVDS connector J17.
The secondary channel is designated with a ‘B’. It maps to the LCD display in a similar
manner to the primary channel.
