Espressif Systems ESP8684 Series, Hardware Design Manuallines, Page: 9 / 28

2 Schematic Checklist
Notice:
CHIP_EN pin must not be left floating.
2.2.3 Power­up and Reset Timing
Figure 4 shows the power-up and reset timing of ESP8684 series of SoCs. Details about the parameters are
listed in Table 1 .
VDDA,
VDDA3P3,
VDD3P3_RTC,
VDD3P3_CPU
CHIP_EN
t0 t1
V
IL_nRST
2.8 V
Figure 4: ESP8684 Power­up and Reset Timing
Table 1: Description of ESP8684 Power­up and Reset Timing Parameters
Min
Parameter Description (
µ
s)
t
0
Time between bringing up the VDDA, VDDA3P3, VDD3P3_RTC, and
VDD3P3_CPU rails, and activating CHIP_EN
50
t
1
Duration of CHIP_EN signal level < V
IL _ nRST
to reset the chip 50
2.3 Flash
ESP8684 series is embedded with 1 MB, 2 MB, or 4 MB flash. It doesn’t need to connect to external flash for
firmware.
2.4 Clock Source
ESP8684 has two clock sources:
• External crystal oscillator clock source
• RTC clock source
2.4.1 External Clock Source (compulsory)
Currently, the ESP8684 firmware only supports 40 MHz crystal or oscillator.
Crystal
The circuit for the crystal is shown in Figure 5 . The specific capacitive values of C1 and C2 depend on further
testing of, and adjustment to, the overall performance of the whole circuit. In order to reduce the drive strength of
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ESP8684 Series Hardware Design Guidelines v1.1