Espressif Systems ESP8684 Series, Hardware Design Manuallines, Page: 19 / 28

3 PCB Layout Design
should be at least 2.0 mm
. It is good practice to add high-density ground via stitching around the clock
trace for better isolation.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator, and
at the end of the clock trace whenever possible, to make sure the ground pad of the capacitor is close to
that of the crystal oscillator.
• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The vias on the power traces on both sides of the crystal clock trace
should be placed as far away from the clock trace as possible, and the two sides of the clock trace should
be surrounded by grounding copper.
• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example large inductance component, and ensure that there is a clean large-area
ground plane around the crystal oscillator.
Figure 14: ESP8684 Crystal Oscillator Layout
3.5 RF
The RF trace is routed as shown highlighted in pink in Figure 15 .
Espressif Systems 19
Submit Documentation Feedback
ESP8684 Series Hardware Design Guidelines v1.1