Espressif Systems ESP8684 Series, Hardware Design Manuallines, Page: 18 / 28

3 PCB Layout Design
connected to the pins on the top layer. There should be at least two vias if the main power traces need to
cross layers. The drill diameter on other power traces should be no smaller than the width of the power
traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 12 . The width of the main
power traces should be no less than 20 mil. The width of the power traces for VDDA3P3 pins should be no
less than 15 mil. Recommended width of other power traces is 10 mil.
• The ESD protection diode is placed next to the power port (circled in red in the top left quarter of Figure 12 ).
The power trace should have a 10 µF capacitor on its way to the chip, to be used in conjunction with a 0.1
µF capacitor. Then the power traces are divided into two ways from here and form a star-shape topology,
thus reducing the coupling between different power pins. Note that all decoupling capacitors should be
placed close to the power pin, and ground vias should be added close to the capacitor’s ground pin to
ensure a short return path.
• As shown in Figure 13 , it is recommended to connect the capacitor to ground in the LC filter circuit near
VDD3P3 pins to the fourth layer through a via, and maintain a keep-out area on other layers.
• The power trace begins at the power entrance and reaches VDDA3P3. It is required to add GND isolation
between this power trace and the GPIO traces on the left, and place vias whenever possible.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a
nine-grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in Figure 12 . This can avoid
tin leakage when soldering the module EPAD to the substrate.
Figure 13: ESP8684 Analog Power Traces in a Four­layer PCB Design
3.4 Crystal Oscillator
Figure 14 shows the reference design of the crystal oscillator. In addition, the following should be noted:
• The crystal oscillator should be placed far from the clock pin to avoid the interference on the chip.
The gap
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ESP8684 Series Hardware Design Guidelines v1.1