Espressif Systems ESP8684 Series, Hardware Design Manuallines, Page: 21 / 28

3 PCB Layout Design
• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR, high-frequency clocks, etc. In
addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded
by ground copper and ground vias.
Figure 17: ESP8684 Stub in a Four­layer PCB Design
3.6 UART
The series resistor on the U0TXD trace needs to be placed close to the chip and away from the crystal. The
U0TXD and U0RXD traces on the top layer should be as short as possible, surrounded by ground copper and
ground vias.
3.7 Typical Layout Problems and Solutions
3.7.1 Q: The current ripple is not large, but the TX performance of RF is rather poor.
Analysis:
The current ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be
tested when ESP8684 is in the normal working mode. The ripple increases when the power gets high in a
different mode.
Generally, the peak-to-peak value of the ripple should be <80 mV when ESP8684 sends MCS7@11n packets,
and <120 mV when ESP8684 sends 11m@11b packets.
Solution:
Add a 10
µ
F filter capacitor to the branch of the power trace (the branch powering the chip’s analog power pin).
The 10 µ F capacitor should be as close to the analog power pin as possible for small and stable current
ripples.
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ESP8684 Series Hardware Design Guidelines v1.1