Espressif Systems ESP8684 Series, Hardware Design Manuallines, Page: 10 / 28

2 Schematic Checklist
the crystal and minimize the impact of crystal harmonics on RF performance, please add a series inductor (initially
of 24 nH) on the XTAL_P clock trace. Note that the accuracy of the selected crystal should be within ±10
ppm.
5 5
4 4
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2 2
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4
CHIP_EN GPIO4 GPIO5 GPIO6
U0RXD
ANT GPIO0 GPIO1 GPIO2 GPIO3
RF_ANT
U0TXD
GPIO2 GPIO3 CHIP_EN
GPIO1
GPIO0
GPIO10
GPIO6
GPIO7
GPIO8
GPIO9
GPIO18 U0RXD U0TXD
GPIO4
GPIO5
GPIO7 GPIO8 GPIO9 GPIO10 GPIO18
GND
VDD33
GND
GND
GND
GND
GND
GND
GND
VDD33
GND
GND
GND
VDD33 VDD33
GND
GND
GND
GND
GND
VDD33
GND
GND
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Friday, October 29, 2021
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Friday, October 29, 2021
C1
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R1 0(1%)
R2
499(1%)
Y1 40MHz
XIN
1
GND
2
XOUT
3
GND
4
L1
2.0nH(0.1nH) C9
TBD
U2
ANT
1
VDDA3P3
2
VDDA3P3
3
GPIO0
4
GPIO1
5
GPIO2
6
CHIP_EN
7
MTMS
9
MTDI
10
VDD3P3_RTC
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
VDD3P3_CPU
17
U0RXD
19
U0TXD
20
XTAL_N
22
XTAL_P
23
GND
25
GPIO3
8
VDDA
24
VDDA
21
GPIO18
18
C6 0.1uF/6.3V(10%)
D1 ESD
C3
1uF/6.3V(20%)
C4
10nF/6.3V(10%)
C10 0.1uF/6.3V(10%)
C7 0.1uF/6.3V(10%)
ANT1 PCB_ANT
1 2
U3
ESP8684-MINI-1
GND
1
3V3
3
IO9
23
NC
4
IO2
5
IO3
6
NC
7
NC
9
NC
10
NC
15
IO10
16
NC
17
IO4
18
IO5
19
NC
32
TXD0
31
RXD0
30
NC
34
NC
33
IO18
26
NC
29
NC
28
NC
27
IO7
21
IO8
22
IO0
12
IO1
13
GND
52
IO6
20
NC
35
NC
24
EPAD
49
GND
2
GND
53
GND
51
GND
50
EN
8
GND
36
GND
37
GND
38
GND
39
GND
40
GND
41
GND
42
GND
43
GND
44
GND
45
GND
46
GND
47
GND
48
GND
14
GND
11
NC
25
C2 TBD
C8
TBD
C12 0.1uF/6.3V(10%)
L2
TBD
C5
10uF/6.3V(20%)
Figure 5: Schematic for the Crystal
Oscillator
If an oscillator is used, its output should be connected to XTAL_P on the chip through a series inductor (a 20 nH
inductor can be used initially). XTAL_N can be floating. Make sure that the oscillator output is stable and its
accuracy is within ±10 ppm. It is recommended that the circuit design for the oscillator is compatible with the
crystal. In case of defects in the circuit design, you can still use the crystal. The circuit for the oscillator is shown
in Figure 6 .
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NC: No component.
The values of C8, L2 and C9
vary with the actual PCB board.
The values of C1 and C2 vary with
the selection of the crystal.
The value of R1 varies with the actual
PCB board.
If using ESP32-C3FN4 or ESP32-C3FH4,
flash is not mounted.
GPIO19
CHIP_EN
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
U0RXD
GPIO18
LNA_IN
GPIO9
GPIO10
GPIO0
GPIO1 SPICS0
SPID
SPIQ
SPICLK
SPIWP
SPIHD
GPIO2
GPIO3
RF_ANT
U0TXD
SPICLK
SPICS0
SPIHD SPIWP
SPID
SPIQ
XTAL_P
GND
VDD33
GND
GND
GND GND GND
GND GND
GND
VDD33
GND GND GND
VDD33
VDD_SPI
VDD33
GND
VDD_SPI
GND
GND
GND GND
GND
VDD33
GND
C1
TBD
C9
TBD
R4 0
U3 FLASH-3V3
/CS
1
DO
2
/WP
3
G
N
D
4
DI
5
CLK
6
/HOLD
7
V
C
C
8
L3
TBD
R7 0
R6 0
ANT1
PCB_ANT
1
2
R
1
0
C12
0.1uF
C3
1uF
C10
0.1uF
R5 0
R1 0
R3 0
R2 499
C1
10nF
C8
TBD
C2
TBD
L1 2.0nH
C6
0.1uF
Y1
40MHz(±10ppm)
VCC
4
NC
1
GND
2
OUT
3
C5
10uF
L2
TBD
C7
1uF
C4
10nF
U2 ESP32-C3
LNA_IN
1
VDD3P3
2
VDD3P3
3
XTAL_32K_P
4
XTAL_32K_N
5
GPIO2
6
CHIP_EN
7
M
T
M
S
9
M
T
D
I
1
0
V
D
D
3
P
3
_
R
T
C
1
1
M
T
C
K
1
2
M
T
D
O
1
3
G
P
IO
8
1
4
G
P
IO
9
1
5
G
P
IO
1
0
1
6
VDD3P3_CPU
17
VDD_SPI
18
SPIHD
19
SPIWP
20
SPICS0
21
SPICLK
22
SPID
23
SPIQ
24
U
0
R
X
D
2
7
U
0
T
X
D
2
8
X
T
A
L
_
N
2
9
X
T
A
L
_
P
3
0
G
N
D
3
3
GPIO3
8
V
D
D
A
3
2
V
D
D
A
3
1
G
P
IO
1
9
2
6
G
P
IO
1
8
2
5
C11
1uF
R8
10K
U1
40MHz(±10ppm)
X
IN
1
G
N
D
2
X
O
U
T
3
G
N
D
4
Figure 6: Schematic for the Oscillator
Notice:
Defects in the manufacturing of crystal and oscillators (for example, large frequency deviation of more than ±10 ppm,
unstable performance within operating temperature range, etc) may lead to the malfunction of ESP8684, resulting in a
decrease of the RF performance.
2.4.2 RTC (optional)
ESP8684 supports an external clock signal (e.g., an oscillator) input through GPIO0 to act as the RTC sleep
clock and the typical clock frequency is 32.768 kHz. The amplitude of the input clock signal should be the same
as the amplitude requirement of the GPIO input signal.
2.5 RF
A π -type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network. The parameters of the components in the matching network are
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ESP8684 Series Hardware Design Guidelines v1.1