ESD electronic CAN-PCI/360, Hardware Installation And Technical Data

Page: 11 / 30

Technical Data
Installation and technical data
CAN-PCI/360
Rev. 1.3 8
3.2 DRAM-Equipping
The DRAM-module is controlled by means of the memory controller integrated in the microcontroller
68360. The multiplexing of address lines, however, is the responsibility of its own multiplexers to make
the DRAM also accessible for external PCI-bus masters. The composition of address pairs by the
multiplexer has been selected in a way that the DRAM-module can also be controlled in page mode.
The following table shows the capacities of DRAM-modules which can be used and the formation of
address pairs.
Buffer capacity Address pairs DRAM address
row address column address
1 Mbyte
2 Mbyte A11 A2 MA2
A12 A3 MA3
A13 A4 MA4
A14 A5 MA5
A15 A6 MA6
A16 A7 MA7
A17 A8 MA8
A18 A9 MA9
A19 A10 MA10
4 Mbyte
8 Mbyte A20 A21 MA11
16 Mbyte
32 Mbyte A22 A23 MA12
64 Mbyte
128 Mbyte
A24 A25 MA13
Table 3.5.1:
Formation of address pairs
3.3 Timekeeper
The timekeeper offers battery-buffered memory capacity in SRAM-technology. As an additional
function it has got an internal counter with a time basis of one second. The quartz required for this has
been integrated into the case of the battery which can be plugged on. The counter format corresponds
to the date and time coded in BCD format with separate values for year, month, day, weekday, hour,
minute and second. These values are read by reading accesses to particular address areas.
The eight data lines of the timekeeper are connected to the local data lines D24...D31 of the
microcontroller 68360.