5 OPERaTIOnS anD FUnCTIOnS OF THE S5U1C63000H6
S5U1C63000H6 ManUal
EPSOn
15
(S1C63 Family In-Circuit Emulator)
(7) Register (data) break
The register (data) value after a break occurs may differ from the value set as a register (data) break condition.
The following shows an example if a break condition has been set so that a break will occur when the A register
is set to 5, and when the S1C63000 CPU has executed the sequence in the timing chart shown below to set the A
register to 5 and 6:
ld %a, 5
ld %a, 6
5
6
ICE monitor command ICE monitor command
CLK
Instruction execution
A register
ICE data judgment point
<1>
<2>
<3>
Figure 5.13.2 Example of Register Break
The S5U1C63000H6 judges the register data at the points indicated with a “
↑
.” It judges that the A register is
“5” at the point of <2>, and the register break condition is met at the same time. However, the S1C63000 CPU
is executing the following “ld %a, 6” instruction at this point and the break occurs after the A register is set to
“6.” Therefore, “6” is read from the A register after the break has occurred. This is also applied to the break by
accessing to undefined area function.
(8) Register (data) break and hardware interrupt
If a hardware interrupt occurs when the register (data) break condition described in Item (7) is met, register (data)
break will occur at the top address of the interrupt handler routine. The following shows an example when a
hardware interrupt factor occurs while the S1C63000 CPU is executing the sequence in the timing chart shown
below to set the A register to 5 and 6, if a break condition has been set so that a register break will occur when
the A register is set to 5:
ld %a, 5
ld %a, 6
5
6
CLK
Instruction execution
A register
Interrupt factor
IACK
ICE data judgment point
<1>
<2>
<3>
Figure 5.13.3 Example When a Register Break and an Interrupt Occur Simultaneously
In the timing chart above, if an interrupt factor occurs (falling edge) at the point of <1>, the S1C63000 CPU
outputs the IACK signal to indicate that an interrupt acknowledgment cycle is executed. The interrupt process-
ing cannot be stopped while IACK is at low level. Therefore, the S5U1C63000H6 cannot disable the interrupt
even if the register break condition (A register = “5”) is met at the point of <2>, as IACK is at low level. The
register break will occur after jumping to the interrupt vector address.
