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Epson Research and Development

Vancouver Design Center

S1D13706

Hardware Functional Specification

X31B-A-001-08

Issue Date: 01/11/13

bits 9-0

Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for panels in 1 line resolution.

For passive LCD panels these bits must be set to 00h.

For TFT panels, VDPS is calculated using the following formula.

VDPS = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)

Note

1

 This register must be programmed such that the following formula is valid.

VDPS + VDP < VT

2

 For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-

face” on page 56.

bit 7

FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must 
be set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the 
panel (typically FPLINE or LP).
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.

bits 6-0

FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The 
horizontal sync signal is typically FPLINE or LP, depending on the panel type.

FPLINE Pulse Width in number of pixels = (REG[20h] bits 6:0) + 1

Note

For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 56.

Vertical Display Period Start Position Register 0
REG[1Eh]

Read/Write

Vertical Display Period Start Position Bits 7-0

7

6

5

4

3

2

1

0

Vertical Display Period Start Position Register 1
REG[1Fh]

Read/Write

n/a

Vertical Display Period Start 

Position Bits 9-8

7

6

5

4

3

2

1

0

FPLINE Pulse Width Register
REG[20h]

Read/Write

FPLINE Pulse 

Polarity

FPLINE Pulse Width Bits 6-0

7

6

5

4

3

2

1

0

Summary of Contents for S1D13706

Page 1: ...but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corp...

Page 2: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 TECHNICAL MANUAL X31B Q 001 06 Issue Date 01 04 17 THIS PAGE LEFT BLANK ...

Page 3: ...s Technical Support Customer Training Design Assistance Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2...

Page 4: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 TECHNICAL MANUAL X31B Q 001 06 Issue Date 01 04 17 THIS PAGE LEFT BLANK ...

Page 5: ...rfor mance bandwidth into display memory allowing for fast screen updates Products requiring a rotated display image can take advantage of the SwivelViewTM feature which provides hardware rotation of the display memory transparent to the software application The S1D13706 also provides support for Picture in Picture Plus a variable size Overlay window The S1D13706 provides impressive support for Pa...

Page 6: ...ws CE Display Driver CPU Independent Software Utilities VXWorks TornadoTM Display Driver Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trad...

Page 7: ...ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epso...

Page 8: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 THIS PAGE LEFT BLANK ...

Page 9: ... 18 4 2 Pinout Diagram CFLGA 104pin 19 4 3 Pinout Diagram Die Form 20 4 4 Pin Descriptions 22 4 4 1 Host Interface 22 4 4 2 LCD Interface 26 4 4 3 Clock Input 28 4 4 4 Miscellaneous 28 4 4 5 Power And Ground 28 4 5 Summary of Configuration Options 29 4 6 Host Bus Interface Pin Mapping 30 4 7 LCD Interface Pin Mapping 31 5 D C Characteristics 32 6 A C Characteristics 33 6 1 Clock Timing 33 6 1 1 In...

Page 10: ...ming 64 6 4 5 Single Color 8 Bit Panel Timing Format 1 66 6 4 6 Single Color 8 Bit Panel Timing Format 2 68 6 4 7 Single Color 16 Bit Panel Timing 70 6 4 8 Generic TFT Panel Timing 72 6 4 9 9 12 18 Bit TFT Panel Timing 73 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx 76 6 4 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 80 6 4 12 160x240 Epson D TFD Panel Timing e g ...

Page 11: ...132 11 1 Monochrome Modes 132 11 2 Color Modes 134 12 SwivelView 138 12 1 Concept 138 12 2 90 SwivelView 138 12 2 1 Register Programming 139 12 3 180 SwivelView 140 12 3 1 Register Programming 140 12 4 270 SwivelView 141 12 4 1 Register Programming 142 13 Picture in Picture Plus PIP 143 13 1 Concept 143 13 2 With SwivelView Enabled 144 13 2 1 SwivelView 90 144 13 2 2 SwivelView 180 144 13 2 3 Swiv...

Page 12: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 THIS PAGE LEFT BLANK ...

Page 13: ...k Input Requirements for CLKI2 34 Table 6 4 Internal Clock Requirements 35 Table 6 5 Generic 1 Interface Timing 37 Table 6 6 Generic 2 Interface Timing 39 Table 6 7 Hitachi SH 4 Interface Timing 41 Table 6 8 Hitachi SH 3 Interface Timing 43 Table 6 9 Motorola MC68K 1 Interface Timing 45 Table 6 10 Motorola MC68K 2 Interface Timing 47 Table 6 11 Motorola REDCAP2 Interface Timing 49 Table 6 12 Motor...

Page 14: ...onship between MCLK and PCLK 92 Table 7 5 PWMCLK Clock Selection 92 Table 7 6 S1D13706 Internal Clock Requirements 94 Table 8 1 S1D13706 Register Set 95 Table 8 2 MCLK Divide Selection 97 Table 8 3 PCLK Divide Selection 98 Table 8 4 PCLK Source Selection 98 Table 8 5 Panel Data Width Selection 102 Table 8 6 Active Panel Resolution Selection 102 Table 8 7 LCD Panel Type Selection 102 Table 8 8 Inve...

Page 15: ... Timing 40 Figure 6 5 Hitachi SH 3 Interface Timing 42 Figure 6 6 Motorola MC68K 1 Interface Timing 44 Figure 6 7 Motorola MC68K 2 Interface Timing 46 Figure 6 8 Motorola REDCAP2 Interface Timing 48 Figure 6 9 Motorola DragonBall Interface with DTACK Timing 50 Figure 6 10 Motorola DragonBall Interface without DTACK Timing 52 Figure 6 11 Passive TFT Power On Sequence Timing 54 Figure 6 12 Passive T...

Page 16: ...31 Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 132 Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path 132 Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path 133 Figure 11 4 8 Bit per pixel Monochrome Mode Data Output Path 133 Figure 11 5 1 Bit Per Pixel Color Mode Data Output Path 134 Figure 11 6 2 Bit Per Pixel Color Mode Data Output Path 135 Figure 11 7 4 Bit...

Page 17: ...buffer While supporting all other panel types the S1D13706 is the only LCD controller to directly interface to both the Epson D TFD and the Sharp HR TFT family of products thus removing the requirement of an external Timing Control IC This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets such as Mobile Communications devices and P...

Page 18: ...otorola REDCAP2 no WAIT signal 8 bit processor support with glue logic Fixed low latency CPU access times Registers are memory mapped M R input selects between memory and register address space The complete 80K byte display buffer is directly and contiguously available through the 17 bit address bus Single level CPU write buffer 2 3 Display Support Single panel single drive passive displays 4 8 bi...

Page 19: ...clockwise hardware rotation of display image Picture in Picture Plus displays a variable size window overlaid over background image Double Buffering Multi pages provides smooth animation and instantaneous screen updates 2 6 Clock Source Two clock inputs CLKI and CLKI2 It is possible to use one clock input only Bus clock is derived from CLKI and can be internally divided by 2 3 or 4 Memory clock is...

Page 20: ...15 0 CLKI2 Oscillator FPLINE FPFRAME FPSHIFT MOD D 15 0 16 bit Generic 1 BUS RESET D 15 0 RD0 WAIT A 16 1 BUSCLK RD WR AB 16 1 DB 15 0 WE1 RD M R CS CLKI WAIT RESET A 27 17 CSn WE1 GPO Decoder WE0 WE0 Single LCD Display Bias Power BS HIOVDD RD1 VSS AB0 S1D13706 FPLINE FPFRAME FPSHIFT DRDY FPDAT 8 0 CLKI2 Oscillator FPLINE FPFRAME FPSHIFT DRDY D 8 0 9 bit Generic 2 BUS RESET D 15 0 RD WAIT A 16 0 B...

Page 21: ...T DRDY D 9 0 12 bit SH 4 BUS RESET WE0 D 15 0 BS RD WR RD RDY A 16 1 CKIO WE0 RD WR AB 16 1 DB 15 0 WE1 BS RD M R CS CLKI WAIT RESET A 25 17 CSn WE1 GPO CLKI2 Oscillator TFT Display Bias Power FPDAT12 FPDAT15 D10 D11 Decoder VSS AB0 S1D13706 FPLINE FPFRAME FPSHIFT DRDY FPDAT 17 0 FPLINE FPFRAME FPSHIFT DRDY D 17 0 18 bit SH 3 BUS RESET WE0 D 15 0 BS RD WR RD WAIT A 16 1 CKIO WE0 RD WR AB 16 1 DB 1...

Page 22: ...R W DTACK A 16 1 CLK AB0 RD WR AB 16 1 DB 15 0 WE1 BS M R CS CLKI WAIT RESET A 23 17 FC0 FC1 Decoder Decoder UDS GPO CLKI2 Oscillator HR TFT Display Bias Power RD WE0 HIOVDD GPIO0 GPIO1 GPIO2 GPIO3 PS CLS REV SPL S1D13706 FPSHIFT FPFRAME DRDY GPIO0 FPDAT 17 0 XSCL DY GCP XINH D 17 0 18 bit MC68K 2 BUS RESET SIZ0 D 31 16 AS R W SIZ1 DSACK1 A 16 0 CLK WE0 RD WR AB 16 0 DB 15 0 WE1 BS RD M R CS CLKI ...

Page 23: ...D D 3 0 4 bit REDCAP2 BUS RESET_OUT EB1 D 15 0 R W OE A 16 1 CLK WE0 RD WR AB 16 1 DB 15 0 WE1 BS RD M R CS CLKI RESET A 21 17 Decoder EB0 GPO CLKI2 Oscillator Single LCD Bias Power CSn Note CSn can be any of CS0 CS4 HIOVDD Display VSS AB0 S1D13706 FPFRAME FPSHIFT FPLINE DRDY FPDAT 7 0 FPFRAME FPSHIFT FPLINE MOD D 7 0 8 bit MC68EZ328 RESET D 15 0 OE DTACK A 16 1 CLKO RD WR AB 16 1 DB 15 0 WE1 RD M...

Page 24: ... 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 TESTEN CNF0 CNF1 CNF2 CNF3 CNF4 CNF5 CNF6 CNF7 DB7 DB5 DB4 DB3 DB2 DB1 DB0 VSS NIOVDD PWMOUT GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CVOUT GPO S1D13706 AB5 VSS AB4 COREVDD AB3 AB2 AB1 AB0 CS BS RD WE0 WE1 RD WR RESET VSS CLKI HIOVDD WAIT ...

Page 25: ... GPIO3 PWMOUT DB1 DB5 DB7 DB11 HIOVDD H FPDAT1 FPDAT0 FPSHIFT FPDAT2 DRDY GPIO1 DB3 DB10 DB13 DB14 DB12 G FPDAT5 FPDAT4 FPDAT3 FPDAT6 VSS NC VSS WE1 CLKI DB15 WAIT F FPDAT10 FPDAT7 FPDAT8 VSS VSS NC NC VSS BS RD WR RESET E FPDAT11 FPDAT9 FPDAT13 FPDAT16 VSS NC VSS AB1 M R WE0 RD D NIOVDD FPDAT12 FPDAT14 CNF7 CNF3 AB13 AB11 AB7 AB3 CS AB0 C NC FPDAT15 FPDAT17 CNF5 CNF1 TESTEN AB14 AB9 AB5 AB2 HIOVD...

Page 26: ...3 4 3 Pinout Diagram Die Form Figure 4 3 Pinout Diagram Die Form S1D13706D00A Chip Size 5 88 x 6 55 mm PAD size 68 x 68 µm Unusable Pad Unusable Pad DIE No X5534D 1 5 10 40 35 30 25 20 15 75 70 65 60 55 50 45 115 110 105 100 85 80 95 90 120 125 130 135 140 145 150 155 160 165 170 180 185 190 195 200 210 205 175 220 225 230 235 215 Y X 0 0 ...

Page 27: ...T13 1512 3149 21 48 DB12 1680 3149 71 167 FPDAT14 1680 3149 22 50 DB11 1848 3149 72 169 FPDAT15 1848 3149 23 53 DB10 2100 3149 73 172 FPDAT16 2100 3149 24 55 DB9 2331 3149 74 174 FPDAT17 2331 3149 25 58 VSS 2813 2478 75 177 VSS 2813 2478 26 60 HVDD 2813 2310 76 179 HVDD 2813 2310 27 62 DB8 2813 2142 77 181 CLKI2 2813 2142 28 65 DB7 2813 1890 78 184 CNF7 2813 1890 29 67 DB6 2813 1722 79 186 CNF6 28...

Page 28: ...h pull down resistor typical value of 50Ω at 3 3V Hi Z High Impedance Table 4 3 Host Interface Pin Descriptions Pin Name Type Pin Cell IO Voltage RESET State Description AB0 I 5 LIS HIOVDD 0 This input pin has multiple functions For Generic 1 this pin is not used and should be connected to VSS For Generic 2 this pin inputs system address bit 0 A0 For SH 3 SH 4 this pin is not used and should be co...

Page 29: ... byte enable signal for the D 7 0 data byte EB1 For DragonBall this pin inputs the byte enable signal for the D 7 0 data byte LWE See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary WE1 I 11 LIS HIOVDD 1 This input pin has multiple functions For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 For Generic 2 this pin inputs the byte enable signal for the...

Page 30: ...be tied to HIO VDD For SH 3 SH 4 this pin inputs the RD WR signal The S1D13706 needs this signal for early decode of the bus cycle For MC68K 1 this pin inputs the R W signal For MC68K 2 this pin inputs the R W signal For REDCAP2 this pin inputs the R W signal For DragonBall this pin must be tied to HIO VDD See Table 4 9 Host Bus Interface Pin Mapping on page 30 for summary RD I 9 LIS HIOVDD 1 This...

Page 31: ...nal WAIT For Generic 2 this pin outputs the wait signal WAIT For SH 3 mode this pin outputs the wait request signal WAIT For SH 4 mode this pin outputs the device ready signal RDY For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 For REDCAP2 this pin is unused Hi Z For DragonBall this pin outputs...

Page 32: ... O 54 LB3P NIOVDD 0 This output pin has multiple functions Shift Clock CLK for Sharp HR TFT XSCL for Epson D TFD See Table 4 10 LCD Interface Pin Mapping on page 31 for summary DRDY O 48 LO3 NIOVDD 0 This output pin has multiple functions Display enable DRDY for TFT panels 2nd shift clock FPSHIFT2 for passive LCD with Format 1 interface GCP for Epson D TFD LCD backplane bias signal MOD for all oth...

Page 33: ...nctions RES for Epson D TFD General purpose IO pin 4 GPIO4 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary GPIO5 IO 40 LB3M NIOVDD 0 This pin has multiple functions DD_P1 for Epson D TFD General purpose IO pin 5 GPIO5 See Table 4 10 LCD Interface Pin Mapping on page 31 for summary GPIO6 IO 39 LB3M NIOVDD 0 This pin has multiple functions YSCLD for Epson D TFD General purpose IO pin...

Page 34: ...s are used for configuration of the S1D13706 and must be connected directly to IO VDD or VSS GPO O 47 LO3 NIOVDD 0 General Purpose Output possibly used for controlling the LCD power It may also be used for the MOD control signal of the Sharp HR TFT panel TESTEN I 86 T1 NIOVDD 0 Test Enable input used for production test only has type 1 pull down resistor with a typical value of 50Ω at 3 3V Table 4...

Page 35: ...s follows CNF4 CNF2 CNF1 CNF0 Host Bus 1 0 0 0 SH 4 SH 3 interface Big Endian 0 0 0 0 SH 4 SH 3 interface Little Endian 1 0 0 1 MC68K 1 Big Endian 0 0 0 1 Reserved 1 0 1 0 MC68K 2 Big Endian 0 0 1 0 Reserved 1 0 1 1 Generic 1 Big Endian 0 0 1 1 Generic 1 Little Endian 1 1 0 0 Reserved 0 1 0 0 Generic 2 Little Endian 1 1 0 1 REDCAP2 Big Endian 0 1 0 1 Reserved 1 1 1 0 DragonBall MC68EZ328 MC68VZ328...

Page 36: ...la MC68K 1 Motorola MC68K 2 Motorola REDCAP2 Motorola MC68EZ328 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 AB0 A01 A0 A01 LDS A0 A01 A01 DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 2 D 15 0 D 15 0 CS External Decode CSn External Decode CSn CSX M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLKO BS Connected to VDD BS AS AS Connected to VDD RD WR RD1 Conne...

Page 37: ... D0 D4 D0 R2 2 D4 R3 2 D4 R2 2 D8 B5 2 G1 G2 G4 G4 G4 FPDAT5 D1 D5 D1 B1 2 D5 G2 2 D5 B1 2 D9 R5 2 G0 G1 G3 G3 G3 FPDAT6 D2 D6 D2 G1 2 D6 B1 2 D6 G1 2 D10 G4 2 B2 B3 B5 B5 B5 FPDAT7 D3 D7 D3 R1 2 D7 R1 2 D7 R1 2 D11 B3 2 B1 B2 B4 B4 B4 FPDAT8 driven 0 driven 0 driven 0 driven 0 driven 0 D4 G3 2 B0 B1 B3 B3 B3 FPDAT9 driven 0 driven 0 driven 0 driven 0 driven 0 D5 B2 2 driven 0 R0 R2 R2 R2 FPDAT10 ...

Page 38: ...ltage VSS 0 V 1 8 2 0 2 2 V 3 0 3 3 3 6 V NIO VDD Supply Voltage VSS 0 V 3 0 3 3 3 6 V VIN Input Voltage VSS IO VDD V TOPR Operating Temperature 40 25 85 C Table 5 3 Electrical Characteristics for VDD 3 3V typical Symbol Parameter Condition Min Typ Max Units IDDS Quiescent Current Quiescent Conditions 170 µA IIZ Input Leakage Current 1 1 µA IOZ Output Leakage Current 1 1 µA VOH High Level Output V...

Page 39: ...m internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Symbol Parameter 2 0V 3 3V Units Min Max Min Max fOSC Input Clock Frequency CLKI 40 100 MHz TOSC Input Clock period CLKI 1 fOSC 1 fOSC ns tPW...

Page 40: ...ements Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Symbol Parameter 2 0V 3 3V Units Min Max Min Max fOSC Input Clock Frequency CLKI 20 66 MHz TOSC Input Clock period CLKI 1 fOSC 1 fOSC ns tPWH Input Clock Pulse Width High CLKI 3 3 ns tPWL Input Clock Pulse Width Low CLKI 3 3 ns tf Input Clock Fall Time 10 90 5 5 ns tr Input Clock Rise Time 10 90 5 5 ns Table 6 3 Clock In...

Page 41: ... 1 2 Internal Clocks Note For further information on internal clocks refer to Section 7 Clocks on page 90 Table 6 4 Internal Clock Requirements Symbol Parameter 2 0V 3 3V Units Min Max Min Max fBCLK Bus Clock frequency 20 66 MHz fMCLK Memory Clock frequency 20 50 MHz fPCLK Pixel Clock frequency 20 50 MHz fPWMCLK PWM Clock frequency 20 66 MHz ...

Page 42: ...llowing section includes CPU interface AC Timing for both 2 0V and 3 3V The 2 0V timings are based on HIO VDD Core VDD 2 0V The 3 3V timings are based on HIO VDD Core VDD 3 3V 6 2 1 Generic 1 Interface Timing Figure 6 2 Generic 1 Interface Timing A 16 1 RD0 RD1 D 15 0 write M R WAIT CLK TCLK t1 t2 t3 t11 t9 t10 WE0 WE1 t13 D 15 0 read t4 t6 t12 t14 t15 CS t5 t8 t7 VALID ...

Page 43: ... edge 0 1 ns t6 CS hold from either RD0 RD1 or WE0 WE1 rising edge 0 0 ns t7a RD0 RD1 WE0 WE1 asserted for MCLK BCLK 8 5 8 5 TCLK t7b RD0 RD1 WE0 WE1 asserted for MCLK BCLK 2 11 5 11 5 TCLK t7c RD0 RD1 WE0 WE1 asserted for MCLK BCLK 3 13 5 13 5 TCLK t7d RD0 RD1 WE0 WE1 asserted for MCLK BCLK 4 17 5 17 5 TCLK t8 RD0 RD1 WE0 WE1 setup to CLK rising edge 2 1 ns t9 Falling edge of either RD0 RD1 or WE...

Page 44: ...are Functional Specification X31B A 001 08 Issue Date 01 11 13 6 2 2 Generic 2 Interface Timing e g ISA Figure 6 3 Generic 2 Interface Timing MEMR SD 15 0 write SA 16 0 IOCHRDY BUSCLK TBUSCLK t1 t2 t3 t11 t9 t10 MEMW t13 SD 15 0 read t4 t6 t12 t14 t15 CS t5 t8 M R SBHE t7 VALID ...

Page 45: ...S setup to BUSCLK rising edge 0 1 ns t6 CS hold from either MEMR or MEMW rising edge 0 0 ns t7a MEMR MEMW asserted for MCLK BCLK 8 5 8 TBUSCLK t7b MEMR MEMW asserted for MCLK BCLK 2 11 5 11 TBUSCLK t7c MEMR MEMW asserted for MCLK BCLK 3 13 5 13 TBUSCLK t7d MEMR MEMW asserted for MCLK BCLK 4 17 5 17 TBUSCLK t8 MEMR or MEMW setup to BUSCLK rising edge 2 1 ns t9 Falling edge of either MEMR or MEMW to...

Page 46: ...Specification X31B A 001 08 Issue Date 01 11 13 6 2 3 Hitachi SH 4 Interface Timing Figure 6 4 Hitachi SH 4 Interface Timing TCKIO t1 t2 t3 t13 t11 t17 t4 t5 t6 t7 t10 t12 t18 t16 CKIO A 16 1 M R CSn RD WR RD D 15 0 BS RDY WEn D 15 0 VALID write read t14 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z t15 t8 t9 ...

Page 47: ...Sn 0 0 ns t5 BS setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 CSn high setup to CKIO 0 2 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 TCKIO t9b RD or WEn asserted for MCLK BCLK 2 11 5 11 5 TCKIO t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 TCKIO t9d RD or WEn asserted for MCLK BCLK 4 18 5 18 5 TCKIO t10 Falling edge RD to D 15 0 driven read cycle 5 24 3 12 ns t11 Fall...

Page 48: ... Specification X31B A 001 08 Issue Date 01 11 13 6 2 4 Hitachi SH 3 Interface Timing Figure 6 5 Hitachi SH 3 Interface Timing TCKIO t1 t2 t3 t11 t12 t16 t8 t5 t6 t7 t10 t13 t17 t14 t15 CKIO A 16 1 M R CSn RD WR RD D 15 0 BS WAIT WEn D 15 0 Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z VALID write read t4 t9 ...

Page 49: ...Sn high setup to CKIO 0 1 ns t5 BS setup 3 1 ns t6 BS hold 7 2 ns t7 CSn setup 0 1 ns t8 A 16 1 M R RD WR hold from CS 0 0 ns t9a RD or WEn asserted for MCLK BCLK max MCLK 50MHz 8 5 8 5 TCKIO t9b RD or WEn asserted for MCLK BCLK 2 11 5 11 5 TCKIO t9c RD or WEn asserted for MCLK BCLK 3 13 5 13 5 TCKIO t9d RD or WEn asserted for MCLK BCLK 4 18 5 18 5 TCKIO t10 Falling edge RD to D 15 0 driven read c...

Page 50: ...Specification X31B A 001 08 Issue Date 01 11 13 6 2 5 Motorola MC68K 1 Interface Timing e g MC68000 Figure 6 6 Motorola MC68K 1 Interface Timing A 16 1 AS UDS D 15 0 write M R R W DTACK CLK TCLK t1 t2 t3 t16 t13 CS t6 t15 t4 t11 LDS t17 t18 D 15 0 read t19 t20 t21 t14 t9 t12 t5 t8 t10 t7 VALID ...

Page 51: ...CLK 2 11 11 TCLK t7c AS asserted for MCLK BCLK 3 13 13 TCLK t7d AS asserted for MCLK BCLK 4 18 18 TCLK t8 AS setup to CLK rising edge while CS AS UDS LDS 0 1 1 ns t9 AS setup to CLK rising edge 1 2 ns t10 UDS LDS setup to CLK rising edge while CS AS UDS LDS 0 3 1 ns t11 UDS LDS high setup to CLK rising edge 3 2 ns t12 First CLK rising edge where AS 1 to DTACK high impedance 5 40 3 14 ns t13 R W se...

Page 52: ...e g MC68030 Figure 6 7 Motorola MC68K 2 Interface Timing Note For information on the implementation of the Motorola 68K 2 Host Bus Interface see Interfacing To The Motorola MC68030 Microprocessor document number X31B G 013 xx A 16 0 AS DS D 31 16 write M R SIZ 1 0 R W DSACK1 CLK TCLK t1 t2 t3 t16 t13 CS t6 t14 t4 D 31 16 read t12 t17 t18 t15 t19 t20 t21 t9 t5 t8 t10 t11 t7 VALID ...

Page 53: ...S asserted for MCLK BCLK 2 11 11 TCLK t7c AS asserted for MCLK BCLK 3 13 13 TCLK t7d AS asserted for MCLK BCLK 4 18 18 TCLK t8 AS falling edge to CLK rising edge 1 1 ns t9 AS rising edge to CLK rising edge 1 3 ns t10 DS falling edge to CLK rising edge 1 1 ns t11 DS setup to CLK rising edge 1 3 ns t12 First CLK where AS 1 to DSACK1 high impedance 5 40 3 14 ns t13 R W setup to CLK rising edge before...

Page 54: ...Motorola REDCAP2 Interface Timing Note For further information on implementing the REDCAP2 microprocessor see Interfac ing to the Motorola REDCAP2 DSP with Integrated MCU document number X31B G 013 xx TCKO t1 t2 CKO A 16 1 OE D 15 0 EB0 D 15 0 Hi Z Hi Z Hi Z Hi Z VALID write read VALID t3 t4 t12 t14 t13 t9 t8 t6 t7 EB1 EB0 t10 t11 EB1 write read R W CSn t5 Note CSn may be any of CS0 CS4 M R ...

Page 55: ... cycle 1 1 ns t7 EB0 EB1 de asserted to CKO rising edge write cycle 1 4 ns t8 D 15 0 input setup to 3rd CKO rising edge after EB0 or EB1 asserted low write cycle see note 1 1 0 ns t9 D 15 0 input hold from 3rd CKO rising edge after EB0 or EB1 asserted low write cycle 23 8 ns t10 OE EB0 EB1 setup to CKO rising edge read cycle 1 0 ns t11 OE EB0 EB1 hold to CKO rising edge read cycle 1 0 ns t12 D 15 ...

Page 56: ...ssue Date 01 11 13 6 2 8 Motorola DragonBall Interface Timing with DTACK e g MC68EZ328 MC68VZ328 Figure 6 9 Motorola DragonBall Interface with DTACK Timing A 16 1 CSX UWE LWE t2 CLKO DTACK TCLKO write Hi Z Hi Z D 15 0 D 15 0 write read t1 OE read Hi Z Hi Z t10 t8 t3 t6 t7 t17 t16 t14 t4 t11 t18 t19 t15 t13 t9 t12 t5 VALID ...

Page 57: ...rted for MCLK BCLK 2 11 11 11 11 TCLKO t5c CSX asserted for MCLK BCLK 3 13 13 13 13 TCLKO t5d CSX asserted for MCLK BCLK 4 17 17 17 17 TCLKO t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edge to CLKO rising edge 0 0 0 0 ns t8 UWE LWE falling edge to CLKO rising edge 1 0 1 0 ns t9 UWE LWE rising edge to CSX rising edge 0 0 0 0 ns t10 OE falling edge to CLKO rising edge 1 1 1 1 ns t11 OE...

Page 58: ...01 08 Issue Date 01 11 13 6 2 9 Motorola DragonBall Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 Figure 6 10 Motorola DragonBall Interface without DTACK Timing A 16 1 CSX UWE LWE t2 CLKO TCLKO write Hi Z Hi Z D 15 0 D 15 0 write read t1 OE read Hi Z Hi Z t10 t8 t3 t6 t7 t14 t4 t11 t16 t13 t15 t5 t9 t12 VALID ...

Page 59: ...Note 1 13 13 TCLKO t5d CSX asserted for MCLK BCLK 4 CPU wait state register should be programmed to 12 wait states Note 1 Note 1 17 17 TCLKO t6 CSX setup to CLKO rising edge 0 0 0 0 ns t7 CSX rising edge setup to CLKO rising edge 0 0 0 0 ns t8 UWE LWE setup to CLKO rising edge 1 0 1 0 ns t9 UWE LWE rising edge to CSX rising edge 0 0 0 0 ns t10 OE setup to CLKO rising edge 1 1 1 1 ns t11 OE hold fr...

Page 60: ...Panels document number X31B G 011 xx For D TFD Power On Off sequence information see Connecting to the Epson D TFD Panels document number X31B G 012 xx Table 6 14 Passive TFT Power On Sequence Timing Symbol Parameter Min Max Units t1 LCD signals active to LCD bias active Note 1 Note 1 t2 Power Save Mode disabled to LCD signals active 0 20 ns LCD Signals GPO Power Save t1 It is recommended to use t...

Page 61: ...the panel connected Table 6 15 Passive TFT Power Off Sequence Timing Symbol Parameter Min Max Units t1 LCD bias deactivated to LCD signals inactive Note 1 Note 1 t2 Power Save Mode enabled to LCD signals low 0 20 ns LCD Signals GPO t1 It is recommended to use the general purpose output pin GPO to control the LCD bias power The LCD power off sequence is activated by programming the Power Save Mode ...

Page 62: ...ion X31B A 001 08 Issue Date 01 11 13 6 4 Display Interface The timing parameters required to drive a flat panel display are shown below Timing details for each supported panel type are provided in the remainder of this section Figure 6 13 Panel Timing Parameters HT VDP VT VDPS VPW VPS HDP HPW HPS HDPS ...

Page 63: ...ption Derived From Units HT Horizontal Total REG 12h bits 6 0 1 x 8 Ts HDP1 Horizontal Display Period1 REG 14h bits 6 0 1 x 8 HDPS Horizontal Display Period Start Position For STN panels REG 17h bits 1 0 REG 16h bits 7 0 22 For TFT panels REG 17h bits 1 0 REG 16h bits 7 0 5 HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 HPW FPLINE Pulse Width REG 20h bits 6 0 1 VT Vertical Tot...

Page 64: ...D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 6 4 1 Generic STN Panel Timing Figure 6 14 Generic STN Panel Timing FPFRAME VT 1 Frame MOD1 DRDY FPLINE MOD2 DRDY FPLINE VDP VPW HT 1 Line HDPS HDP FPDAT 17 0 FPDAT 17 0 1PCLK FPSHIFT HPW HPS ...

Page 65: ...pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position 22 pixels because REG 17h bits 1 0 REG 16h bits 7 0 0 HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels For passive panels the HDP must be a minimum of 32 pixels and must be increased by multiples of 16 HPS must c...

Page 66: ...ts 7 0 REG 1Dh bits 1 0 REG 1Ch bits 7 0 Lines HDP Horizontal Display Period REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts FPLINE FPSHIFT FPFRAME FPLINE DRDY MOD DRDY MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel FPDAT 7 4 FPDAT6 FPDAT5 FPDAT4 FPDAT7 VDP LINE1 LINE2 LINE3 LINE4 LINE239...

Page 67: ...e note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 ...

Page 68: ...REG 14h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts FPLINE FPSHIFT FPFRAME FPLINE DRDY MOD DRDY MOD Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel FPDAT 7 0 FPDAT6 FPDAT5 FPDAT4 FPDAT7 FPDAT2 FPDAT1 FPDAT0 FPDAT3 HNDP VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2 1 2 1 10 1 634 1 3 1 11...

Page 69: ...e note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t9 FPSHIFT period 8 Ts t10 FPSHIFT pulse width low 4 ...

Page 70: ... Non Display Period HT HDP REG 12h bits 6 0 1 x 8Ts REG 14h bits 6 0 1 x 8Ts FPLINE FPFRAME FPLINE DRDY MOD DRDY MOD FPSHIFT VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 B319 1 R320 1 G320 1 B320 HDP HNDP FPDAT 7 4 FPDAT4 FPDAT5 FPDAT6 FPDAT7 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid...

Page 71: ... Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width low 0 5 Ts t...

Page 72: ...P HNDP FPDAT5 FPDAT6 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 FPDAT7 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Notes Ts Pixel clock period PCLK The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIF...

Page 73: ...dge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t6a FPSHIFT falling edge to FPLINE rising edge note 6 Ts t6b FPSHIFT2 falling edge to FPLINE rising edge note 7 Ts t7a FPSHIFT falling edge to FPLINE falling edge t6a t4 Ts t7b FPSHIFT2 falling edge to FPLINE falling edge t6b t4 Ts t8 FPLINE falling edge to FPSHIFT rising FPSHIFT2 falling edge t14 2 Ts t9 FPSHIFT2 FPSHIFT per...

Page 74: ...s FPLINE FPFRAME FPLINE DRDY MOD DRDY MOD FPSHIFT VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 LINE1 LINE2 VNDP 1 R1 1 G1 1 B1 1 R2 1 G2 1 B2 1 R3 1 G3 1 B3 1 R4 1 G4 1 B4 1 R5 1 G 5 1 B5 1 R6 1 G6 1 B6 1 R7 1 G7 1 B7 1 R8 1 G8 1 B8 1 G318 1 B318 1 R319 1 G319 1 B319 1 R320 1 G320 1 B320 HDP HNDP FPDAT 7 0 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Invalid Invalid Invalid Invalid Inval...

Page 75: ... edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width lo...

Page 76: ...39 1 R5 1 G10 1 B639 1 G1 1 B6 1 R636 1 R2 1 G7 1 B636 1 B2 1 R8 1 G637 1 G3 1 B8 1 R638 1 R4 1 G9 1 B638 1 B4 1 R10 1 G639 1 G5 1 B10 1 R640 1 R6 1 G11 1 B640 1 B11 1 G12 1 R13 1 B13 1 G14 1 R15 1 B15 1 R12 1 B12 1 G13 1 R14 1 B14 1 G15 1 R16 1 B16 1 B5 1 R11 1 G640 1 G16 HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel FPDAT 15 0 FPDAT15 FPDAT9 FPDAT8 FPD...

Page 77: ...e 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t10 FPSHIFT pulse width low 2 Ts t1...

Page 78: ... 0 REG 1Ch bits 7 0 1 lines HT Horizontal Total REG 12h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 23h bits 1 0 REG 22h bits 7 0 1 pixels HPW FPLINE Pulse Width REG 20h bits 6 0 1 pixels HDPS Horizontal Display Period Start Position REG 17h bits 1 0 REG 16h bits 7 0 5 pixels HDP Horizontal Display Period REG 14h bits 6 0 1 x 8 pixels For TFT panels the HDP must be a minimum of 8 pix...

Page 79: ...VNDP2 Lines VNDP2 Vertical Non Display Period 2 VDPS VPS Lines if negative add VT HDP Horizontal Display Period HDP Ts HNDP Horizontal Non Display Period HNDP1 HNDP2 HT HDP Ts HNDP1 Horizontal Non Display Period 1 HDPS HPS Ts if negative add HT HNDP2 Horizontal Non Display Period 2 HPS HDP HDPS Ts if negative add HT FPFRAME FPLINE LINE1 LINE480 1 1 1 2 1 320 FPLINE FPSHIFT DRDY FPDAT 17 0 VDP DRDY...

Page 80: ...6 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 Figure 6 29 TFT A C Timing t3 t5 FPLINE t1 t4 FPFRAME DRDY FPSHIFT 320 t2 FPLINE 2 1 319 t13 t10 t11 t14 t15 t16 t7 t8 t9 t12 FPDAT 17 0 Note DRDY is used to indicate the first pixel t6 invalid invalid ...

Page 81: ...ng edge to FPLINE falling edge phase difference HPS Ts note 1 t4 FPLINE cycle time HT Ts t5 FPLINE pulse width low HPW Ts t6 FPLINE Falling edge to DRDY active note 2 250 Ts t7 DRDY pulse width HDP Ts t8 DRDY falling edge to FPLINE falling edge note 3 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width high 0 5 Ts t11 FPSHIFT pulse width low 0 5 Ts t12 FPLINE setup to FPSHIFT falling edge 0 5 Ts t13...

Page 82: ...1B A 001 08 Issue Date 01 11 13 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx Figure 6 30 160x160 Sharp Direct HR TFT Panel Horizontal Timing FPLINE t2 FPDAT 17 0 t3 t4 t12 t11 GPIO3 GPIO2 t10 t9 FPSHIFT GPIO1 GPIO0 D1 t13 t8 D2 D3 D160 FPLINE t1 FPFRAME t7 SPS LP LP CLK SPL CLS PS REV t5 t6 ...

Page 83: ...T Horizontal Timing Symbol Parameter Min Typ Max Units t1 FPLINE start position 13 Ts note 1 t2 Horizontal total period 180 220 Ts t3 FPLINE width 2 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 5 Ts t8 Horizontal display period 160 Ts t9 FPLINE rising edge to GPIO3 rising edge 4 Ts t10 GPIO3 ...

Page 84: ...dware Functional Specification X31B A 001 08 Issue Date 01 11 13 Figure 6 31 160x160 Sharp Direct HR TFT Panel Vertical Timing t1 FPDAT 17 0 GPIO1 t4 FPFRAME GPIO0 t2 t3 LINE1 LINE2 LINE160 t5 t6 t7 t8 t10 t11 t12 GPIO1 GPIO0 t9 t13 t14 FPLINE FPSHIFT SPS CLS PS LP CLK CLS PS ...

Page 85: ...splay period 160 Lines t4 Vertical sync pulse width 2 Lines t5 FPFRAME falling edge to GPIO1 alternate timing start 5 Lines t6 GPIO1 alternate timing period 4 Lines t7 FPFRAME falling edge to GPIO0 alternate timing start 40 Lines t8 GPIO0 alternate timing period 162 Lines t9 GPIO1 first pulse rising edge to FPLINE rising edge 4 Ts note 1 t10 GPIO1 first pulse width 48 Ts t11 GPIO1 first pulse fall...

Page 86: ...1B A 001 08 Issue Date 01 11 13 6 4 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 Figure 6 32 320x240 Sharp Direct HR TFT Panel Horizontal Timing FPLINE t2 FPDAT 17 0 t3 t4 t12 t11 GPIO3 GPIO2 t10 t9 FPSHIFT GPIO1 GPIO0 D1 t13 t6 D2 D3 D320 FPLINE t1 FPFRAME SPS LP LP CLK SPL CLS PS REV t5 t7 t8 ...

Page 87: ...00 440 Ts t3 FPLINE width 1 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 60 Ts t8 Horizontal display period 320 Ts t9 FPLINE rising edge to GPIO3 rising edge 59 Ts t10 GPIO3 pulse width 1 Ts t11 GPIO1 GPIO0 pulse width 353 Ts t12 GPIO1 rising edge GPIO0 falling edge to FPLINE rise edge 5 Ts t...

Page 88: ... Date 01 11 13 6 4 12 160x240 Epson D TFD Panel Timing e g LF26SCR Figure 6 34 160x240 Epson D TFD Panel Horizontal Timing FPLINE t8 FPDAT 17 0 t1 t2 t10 t13 t9 t14 GPIO4 t10 t16 FPSHIFT GPIO1 GPIO0 GPIO6 GPIO2 GPIO3 GPIO5 1 2 3 4 t17 t11 t17 t7 t12 t12 t11 t15 t9 t4 t3 160 t6 t5 LP XSCL RES YSCL XINH YSCLD FR FRS DD_P1 R G B ...

Page 89: ...tive period 167 Ts t4 FPSHIFT start to first data 4 Ts t5 Horizontal display period 160 Ts t6 Last data to FPSHIFT inactive 3 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts t8 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIO0 pulse widt...

Page 90: ...40 Epson D TFD Panel GCP Horizontal Timing 1 Ts pixel clock period Table 6 29 160x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units t1 Half of the horizontal total period 200 Ts note 1 t2 GCP clock period 1 Ts GPIO4 1 GCP Data Register bit7 Index 00h DRDY 1 0 1 1 0 0 0 bit0 t2 t1 bit7 Index 01h 1 1 Index 00h bit7 RES GCP REG 2Ch ...

Page 91: ...FD Panel Vertical Timing 1 Ts pixel clock period Table 6 30 160x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1 t2 Horizontal total period 400 Ts t3 Vertical display start 400 Ts FPFRAME Vertical Total 250HT FPDAT 17 0 t1 line1 GPIO1 GPIO0 GPIO2 FR odd frame even frame t2 line2 GPIO2 FR t3 DY YSCL XINH R G B ...

Page 92: ... Date 01 11 13 6 4 13 320x240 Epson D TFD Panel Timing e g LF37SQR Figure 6 37 320x240 Epson D TFD Panel Horizontal Timing FPLINE t8 FPDAT 17 0 t1 t2 t10 t13 t9 t14 GPIO4 t10 t16 FPSHIFT GPIO1 GPIO0 GPIO6 GPIO2 GPIO3 GPIO5 1 2 3 4 t17 t11 t17 t7 t12 t12 t11 t15 t9 t4 t3 320 t5 t6 LP XSCL R G B RES YSCL XINH YSCLD FR FRS DD_P1 ...

Page 93: ...tive period 331 Ts t4 FPSHIFT start to first data 6 Ts t5 Horizontal display period 320 Ts t6 Last data to FPSHIFT inactive 5 Ts t7 FPLINE falling edge to GPIO4 first pulse falling edge 1 Ts t8 Horizontal total period 400 Ts t9 GPIO4 first pulse falling edge to second pulse falling edge 200 Ts t10 GPIO4 pulse width 11 Ts t11 GPIO1 pulse width 100 Ts t12 GPIO1 low period 100 Ts t13 GPIO0 pulse widt...

Page 94: ...40 Epson D TFD Panel GCP Horizontal Timing 1 Ts pixel clock period Table 6 32 320x240 Epson D TFD Panel GCP Horizontal Timing Symbol Parameter Min Typ Max Units t1 Half of the horizontal total period 200 Ts note 1 t2 GCP clock period 1 Ts GPIO4 1 GCP Data Register bit7 Index 00h DRDY 1 0 1 1 0 0 0 bit0 t2 t1 bit7 Index 01h 1 1 Index 00h bit7 RES GCP REG 2Ch ...

Page 95: ...FD Panel Vertical Timing 1 Ts pixel clock period Table 6 33 320x240 Epson D TFD Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 FPFRAME pulse width 200 Ts note 1 t2 Horizontal total period 400 Ts t3 Vertical display start 400 Ts FPFRAME Vertical Total 250HT FPDAT 17 0 t1 line1 GPIO1 GPIO0 GPIO2 FR odd frame even frame t2 line2 GPIO2 FR t3 DY YSCL XINH R G B ...

Page 96: ...access the embedded SRAM The S1D13706 is designed with efficient power saving control for clocks clocks are turned off when not used reducing the frequency of MCLK does not necessarily save more power Furthermore reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance For a balance of power saving and performance the MCLK ...

Page 97: ...e frame rates Secondly it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non display periods to lower the frame rate to its optimal value The source clock options for PCLK may be selected as in the following table Table 7 3 PCLK Clock Selection Source Clock Options PCLK Selection MCLK REG 05h 00h MCLK 2 REG 05h 10h MCLK 3 REG 05h 20h MCLK 4 REG 05h 30h MCL...

Page 98: ... Section 8 3 9 Pulse Width Modulation PWM Clock and Contrast Voltage CV Pulse Configuration Registers on page 126 Note The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the back light inverter Table 7 4 Relationship between MCLK and PCLK SwivelView Orientation Color Depth bpp MCLK to PCLK Relationship SwivelV...

Page 99: ...k Selection The following diagram provides a logical representation of the S1D13706 internal clocks Figure 7 1 Clock Selection Note 1 CNF 7 6 must be set at RESET CLKI CLKI2 2 3 4 00 01 10 11 BCLK 2 3 4 00 01 10 11 MCLK 00 01 10 11 2 3 4 000 001 010 011 8 1xx 0 1 PCLK PWMCLK REG 05h bits 1 0 REG B1h bit 0 REG 05h bits 6 4 REG 04h bits 5 4 CNF 7 6 1 ...

Page 100: ...n optional clock see Section 7 1 4 PWMCLK on page 92 Table 7 6 S1D13706 Internal Clock Requirements Function Bus Clock BCLK Memory Clock MCLK Pixel Clock PCLK PWM Clock PWMCLK Register Read Write Required Not Required Not Required Not Required1 Memory Read Write Required Required Not Required Not Required1 Look Up Table Register Read Write Required Required Not Required Not Required1 Software Powe...

Page 101: ... Up Table Red Read Data Register 101 REG 0Fh Look Up Table Read Address Register 101 Panel Configuration Registers REG 10h Panel Type Register 101 REG 11h MOD Rate Register 103 REG 12h Horizontal Total Register 103 REG 14h Horizontal Display Period Register 103 REG 16h Horizontal Display Period Start Position Register 0 104 REG 17h Horizontal Display Period Start Position Register 1 104 REG 18h Ve...

Page 102: ...P Window Y Start Position Register 0 117 REG 89h PIP Window Y Start Position Register 1 117 REG 8Ch PIP Window X End Position Register 0 118 REG 8Dh PIP Window X End Position Register 1 118 REG 90h PIP Window Y End Position Register 0 119 REG 91h PIP Window Y End Position Register 1 119 Miscellaneous Registers REG A0h Power Save Configuration Register 120 REG A1h Reserved 120 REG A2h Reserved 121 ...

Page 103: ... pins CNF 7 0 CNF 7 0 are latched at the rising edge of RESET 8 3 2 Clock Configuration Registers bits 5 4 MCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Memory Clock MCLK from the Bus Clock BCLK bit 0 Reserved This bit must remain at 0 Display Buffer Size Register REG 01h Read Only Display Buffer Size Bits 7 0 7 6 5 4 3 2 1 0 Configuration Readback Register REG 0...

Page 104: ...k Source bits 1 0 PCLK Source Select Bits 1 0 These bits determine the source of the Pixel Clock PCLK Pixel Clock Configuration Register REG 05h Read Write n a PCLK Divide Select Bits 2 0 n a PCLK Source Select Bits 1 0 7 6 5 4 3 2 1 0 Table 8 3 PCLK Divide Selection PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio 000 1 1 001 2 1 010 3 1 011 4 1 1XX 8 1 Table 8 4 PCLK Source Selection ...

Page 105: ... written to the green component of the Look Up Table The data is stored in this register until a write to the LUT Write Address register REG 0Bh moves the data into the Look Up Table Note The LUT entry is updated only when the LUT Write Address Register REG 0Bh is written to bits 7 2 LUT Red Write Data Bits 5 0 This register contains the data to be written to the red component of the Look Up Table...

Page 106: ... the data from the blue component of the Look Up Table The LUT position is controlled by the LUT Read Address Register REG 0Fh This is a read only register Note This register is updated only when the LUT Read Address Register REG 0Fh is writ ten to bits 7 2 LUT Green Read Data Bits 5 0 This register contains the data from the green component of the Look Up Table The LUT position is controlled by t...

Page 107: ... made the LUT Read Ad dress register is automatically updated with the same value 8 3 4 Panel Configuration Registers bit 7 Panel Data Format Select When this bit 0 8 bit single color passive LCD panel data format 1 is selected For AC timing see Section 6 4 5 Single Color 8 Bit Panel Timing Format 1 on page 66 When this bit 1 8 bit single color passive LCD panel data format 2 is selected For AC ti...

Page 108: ...ver all panel configuration registers REG 12h REG 27h still require program ming with the appropriate values for the selected panel For panel AC timing see Section 6 4 Display Interface on page 56 bits 1 0 Panel Type Bits 1 0 These bits select the panel type Table 8 5 Panel Data Width Selection Panel Data Width Bits 1 0 Passive Panel Data Width Size Active Panel Data Width Size 00 4 bit 9 bit 01 8...

Page 109: ... are valid HDPS HDP HT 2 For panel AC timing and timing parameter definitions see Section 6 4 Display Inter face on page 56 bits 6 0 Horizontal Display Period Bits 6 0 These bits specify the LCD panel Horizontal Display Period HDP in 8 pixel resolution The Horizontal Display Period should be less than the Horizontal Total to allow for a suf ficient Horizontal Non Display Period Horizontal Display ...

Page 110: ... 17h bits 1 0 REG 16h bits 7 0 22 For TFT HR TFT D TFD panels HDPS is calculated using the following formula HDPS REG 17h bits 1 0 REG 16h bits 7 0 5 For further information on calculating the HDPS see the specific panel AC Timing in Sec tion 6 4 Display Interface on page 56 Note This register must be programmed such that the following formula is valid HDPS HDP HT Horizontal Display Period Start P...

Page 111: ... Inter face on page 56 bits 9 0 Vertical Display Period Bits 9 0 These bits specify the LCD panel Vertical Display period in 1 line resolution The Vertical Display period should be less than the Vertical Total to allow for a sufficient Vertical Non Display period Vertical Display Period in number of lines REG 1Ch bits 7 0 REG 1Dh bits 1 0 1 Note For panel AC timing and timing parameter definitions...

Page 112: ...1 For TFT panels this bit is set according to the horizontal sync signal of the panel typically FPLINE or LP When this bit 0 the horizontal sync signal is active low When this bit 1 the horizontal sync signal is active high bits 6 0 FPLINE Pulse Width Bits 6 0 These bits specify the width of the panel horizontal sync signal in 1 pixel resolution The horizontal sync signal is typically FPLINE or LP...

Page 113: ...it is set according to the horizontal sync signal of the panel typically FPFRAME SPS or DY When this bit 0 the vertical sync signal is active low When this bit 1 the vertical sync signal is active high bits 2 0 FPFRAME Pulse Width Bits 2 0 These bits specify the width of the panel vertical sync signal in 1 line resolution The ver tical sync signal is typically FPFRAME SPS or DY depending on the pa...

Page 114: ...8 bit GCP data regis ters bits 7 0 D TFD GCP Data Bits 7 0 For D TFD panel only This register stores the data to be written to the GCP data bits and is controlled by the D TFD GCP Index register REG 28h For further information on the use of this register see Connecting to the Epson D TFD Panels document number X31B G 012 xx Note The Panel Type bits REG 10h bits 1 0 must be set to 11 D TFD for the ...

Page 115: ...Table is used 64 shades of gray are available for each position used in the LUT In color modes 64 shades of color are available for each color component resulting in 256K possible color combinations When this bit 0 dithering is enabled for passive LCD panels When this bit 1 dithering is disabled for passive LCD panels Note This bit does not refer to the number of simultaneously displayed colors bu...

Page 116: ... can be enabled CNF3 must be set to 1 at RESET GPIO Pin Input Enable REG A9h bit 7 must be set to 1 GPIO0 Pin IO Configuration REG A8h bit 0 must be set to 0 If Hardware Video Invert is not available i e HR TFT panel is used the video invert function can be controlled by software using REG 70h bit 4 The following table summa rizes the video invert options available Note Video data is inverted afte...

Page 117: ...er 16 bit word to be swapped before sending them to the LCD dis play If the Display Data Byte Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed Note For further information on byte swapping for Big Endian mode see Section 14 Big Endian Bus Interface on page 146 Table 8 9 LCD Bit per pixel Selection Bit per pixel Select Bits 2 0 Color Depth bpp Maximum Number of Av...

Page 118: ...e This bit enables the PIP window within the main window used for the Picture in Picture Plus feature The location of the PIP window within the landscape window is determined by the PIP Window X Position registers REG 84h REG 85h REG 8Ch REG 8Dh and PIP Window Y Position registers REG 88h REG 89h REG 90h REG 91h The PIP window has its own Display Start Address register REG 7Ch REG 7Dh REG 7Eh and ...

Page 119: ...the sec ond double word of the display memory and so on Calculate the Display Start Address as follows Main Window Display Start Address bits 16 0 image address 4 valid only for SwivelView 0 Note For information on setting this register for other SwivelView orientations see Section 12 SwivelView on page 138 Main Window Display Start Address Register 0 REG 74h Read Write Main window Display Start A...

Page 120: ...ress Offset as follows Main Window Line Address Offset bits 9 0 display width in pixels 32 bpp Note A virtual display can be created by programming this register with a value greater than the formula requires When a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image Main Window Line Address Offset Regis...

Page 121: ...se bits are the LCD display s 10 bit address offset from the starting double word of line n to the starting double word of line n 1 for the PIP window Note that this is a 32 bit address increment Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 PIP Window Display Start Address Register 0 REG 7C Read Write PIP Window Display Start Address Bits 7 0 7 6 5 4 3 ...

Page 122: ...sition is incremented by x pixels where x is relative to the current color depth For 90 and 270 SwivelView the X start position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note 1 These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 T...

Page 123: ...sition is incremented in 1 line increments For 90 and 270 SwivelView the Y start position is incremented by y pixels where y is relative to the current color depth Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note 1 These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 Th...

Page 124: ...sition is incremented by x pixels where x is relative to the current color depth For 90 and 270 SwivelView the X end position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note 1 These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 The...

Page 125: ...sition is incremented in 1 line increments For 90 and 270 SwivelView the Y end position is incremented by y pixels where y is relative to the current color depth Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note 1 These bits have no effect unless the PIP Window Enable bit is set to 1 REG 71h bit 4 2 The ...

Page 126: ...turned off Note Memory writes are possible during power save mode because the S1D13706 dynamical ly enables the memory controller for display buffer writes bit 0 Power Save Mode Enable When this bit 1 the software initiated power save mode is enabled When this bit 0 the software initiated power save mode is disabled At reset this bit is set to 1 For a summary of Power Save Mode see Section 15 Powe...

Page 127: ...ved This bit must remain at 0 bits 15 0 Scratch Pad Bits 15 0 This register contains general purpose read write bits These bits have no effect on hardware Reserved REG A2h Read Write Reserved n a Reserved 7 6 5 4 3 2 1 0 Reserved REG A3h Read Write Reserved n a 7 6 5 4 3 2 1 0 Scratch Pad Register 0 REG A4h Read Write Scratch Pad Bits 7 0 7 6 5 4 3 2 1 0 Scratch Pad Register 1 REG A5h Read Write S...

Page 128: ...put pin bit 3 GPIO3 Pin IO Configuration When this bit 0 default GPIO3 is configured as an input pin When this bit 1 GPIO3 is configured as an output pin bit 2 GPIO2 Pin IO Configuration When this bit 0 default GPIO2 is configured as an input pin When this bit 1 GPIO2 is configured as an output pin bit 1 GPIO1 Pin IO Configuration When this bit 0 default GPIO1 is configured as an input pin When th...

Page 129: ...a 0 to this bit drives GPIO5 low When a D TFD panel is not selected REG 10h bits 1 0 and GPIO5 is configured as an input a read from this bit returns the status of GPIO5 When a D TFD panel is enabled REG 10h bits 1 0 11 and a 1 is written to this bit the D TFD signal DD_P1 signal is enabled When a D TFD panel is enabled REG 10h bits 1 0 11 and a 0 is written to this bit the D TFD signal DD_P1 sign...

Page 130: ...this bit drives GPIO2 high and writing a 0 to this bit drives GPIO2 low When neither a D TFD panel or a HR TFT are selected REG 10h bits 1 0 and GPIO2 is configured as an input a read from this bit returns the status of GPIO2 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO2 outputs the FR signal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits ...

Page 131: ...om this bit returns the status of GPIO0 When a D TFD panel is enabled REG 10h bits 1 0 11 GPIO0 outputs the XINH sig nal automatically and writing to this bit has no effect When a HR TFT panel is enabled REG 10h bits 1 0 10 GPIO0 outputs the PS signal automatically and writing to this bit has no effect bit 7 GPO Control This bit controls the General Purpose Output pin Writing a 0 to this bit drive...

Page 132: ...Save Mode is enabled PWM Clock CV Pulse Control Register REG B0h Read Write PWM Clock Force High n a PWM Clock Enable CV Pulse Force High CV Pulse Burst Status RO CV Pulse Burst Start CV Pulse Enable 7 6 5 4 3 2 1 0 Table 8 15 PWM Clock Control Bit 7 Bit 4 Result 0 1 PWM Clock circuitry enabled controlled by REG B1h and REG B3h 0 0 PWMOUT forced low 1 x PWMOUT forced high x don t care PWM Clock Di...

Page 133: ... This is a read only bit A 1 indicates a CV pulse burst is occurring A 0 indicates no CV pulse burst is occurring Software should wait for this bit to clear before starting another burst bit 1 CV Pulse Burst Start A 1 in this bit initiates a single CVOUT pulse burst The number of clock pulses generated is programmable from 1 to 256 The frequency of the pulses is the divided CV Pulse source divided...

Page 134: ...lock is further divided by 2 before it is output at the CVOUT bit 0 PWMCLK Source Select When this bit 0 the clock source for PWMCLK is CLKI When this bit 1 the clock source for PWMCLK is CLKI2 Note For further information on the PWMCLK source select see Section 7 2 Clock Selec tion on page 93 PWM Clock CV Pulse Configuration Register REG B1h Read Write PWM Clock Divide Select Bits 3 0 CV Pulse Di...

Page 135: ...hisRegister 1 bits 7 0 PWMOUT Duty Cycle Bits 7 0 This register determines the duty cycle of the PWMOUT output CV Pulse Burst Length Register REG B2h Read Write CV Pulse Burst Length Bits 7 0 7 6 5 4 3 2 1 0 PWMOUT Duty Cycle Register REG B3h Read Write PWMOUT Duty Cycle Bits 7 0 7 6 5 4 3 2 1 0 Table 8 19 PWMOUT Duty Cycle Select Options PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low 01h ...

Page 136: ...cification X31B A 001 08 Issue Date 01 11 13 9 Frame Rate Calculation The following formula is used to calculate the display frame rate Where fPCLK PClk frequency Hz HT Horizontal Total REG 12h bits 6 0 1 x 8 Pixels VT Vertical Total REG 19h bits 1 0 REG 18h bits 7 0 1 Lines FrameRate fPCLK HT VT ...

Page 137: ...e 0 Byte 1 Byte 2 Panel Display P0P1P2 P3P4P5P6 P7 Panel Display P0P1P2 P3P4P5P6 P7 An Bn Cn Dn En Fn Gn Hn 16 bpp R0 4 Host Address Display Buffer bit 7 bit 0 R0 3 R0 2 R0 1 R0 0 G0 5 G0 4 G0 3 G0 2 G0 1 G0 0 B0 4 B0 3 B0 2 B0 1 B0 0 R1 4 R1 3 R1 2 R1 1 R1 0 G1 5 G1 4 G1 3 G1 2 G1 1 G1 0 B1 4 B1 3 B1 2 B1 1 B1 0 5 6 5 RGB Byte 0 Byte 1 Byte 2 Byte 3 Panel Display P0P1P2 P3P4P5P6 P7 Pn Rn 4 0 Gn 5...

Page 138: ...onochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome Mode Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path Green Look Up Table 256x6 00 01 1 bit per pixel data 6 bit Gray Data from Display Buffer unused Look Up Table entries 00 01 FC FD FE FF G...

Page 139: ...ook Up Table 256x6 0000 0001 4 bit per pixel data 6 bit Gray Data from Display Buffer 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 unused Look Up Table entries 00 01 02 03 FC FD FE FF 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0000 0000 0001 6 bit Gray Data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101...

Page 140: ...ctly mapped for this color depth See Display Data Formats on page 131 11 2 Color Modes 1 Bit Per Pixel Color Figure 11 5 1 Bit Per Pixel Color Mode Data Output Path 1 bit per pixel data from Image Buffer 6 bit Blue Data 0 1 Blue Look Up Table 256x6 00 01 FC FD FE FF 6 bit Red Data 0 1 Red Look Up Table 256x6 00 01 FC FD FE FF 6 bit Green Data 0 1 Green Look Up Table 256x6 00 01 FC FD FE FF unused ...

Page 141: ...olor Figure 11 6 2 Bit Per Pixel Color Mode Data Output Path 2 bit per pixel data from Image Buffer 6 bit Blue Data 00 01 10 11 Blue Look Up Table 256x6 00 01 02 03 FC FD FE FF 6 bit Red Data 00 01 10 11 Red Look Up Table 256x6 00 01 02 03 FC FD FE FF 6 bit Green Data 00 01 10 11 Green Look Up Table 256x6 00 01 02 03 FC FD FE FF unused Look Up Table entries ...

Page 142: ...000 1001 1010 1011 1100 1101 1110 1111 6 bit Green Data 6 bit Blue Data Red Look Up Table 256x6 00 01 02 03 FC FD FE FF 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Green Look Up Table 256x6 00 01 02 03 FC FD FE FF 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 111...

Page 143: ...er 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 F8 F9 FA FB FC FD FE FF 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 6 bit Green Data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 6 bit Blue Data 0000 001...

Page 144: ...age is not actually rotated in the display buffer since there is no address translation during CPU read write The image is rotated during display refresh 12 2 90 SwivelView 90 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is bei...

Page 145: ... Address registers REG 74h REG 75h REG 76h must be programmed with the address of pixel B To calculate the value of the address of pixel B use the following formula assumes 8 bpp color depth Main Window Display Start Address bits 16 0 image address panel height x bpp 8 4 1 0 320 pixels x 8 bpp 8 4 1 79 4Fh Line Address Offset The Main Window Line Address Offset registers REG 78h REG 79h is based o...

Page 146: ... 180 SwivelView Mode Set SwivelView Mode Select bits REG 71h bits 1 0 to 10 Display Start Address The display refresh circuitry starts at pixel D therefore the Main Window Display Start Address registers REG 74h REG 75h REG 76h must be programmed with the address of pixel D To calculate the value of the address of pixel D use the following formula assumes 8 bpp color depth Main Window Display Star...

Page 147: ...ck MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the S1D13706 in the following sense A B C D The display is refreshed by the S1D13706 in the following sense C A D B Figure 12 3 Relationship Between The Screen I...

Page 148: ...4h REG 75h REG 76h must be programmed with the address of pixel C To calculate the value of the address of pixel C use the following formula assumes 8 bpp color depth Main Window Display Start Address bits 16 0 image address panel width 1 x offset x bpp 8 4 0 480 pixels 1 x 320 pixels x 8 bpp 8 4 38320 95B0h Line Address Offset The Main Window Line Address Offset registers REG 78h REG 79h is based...

Page 149: ...trolled through the PIP window control registers REG 7Ch through REG 91h The PIP window retains the same color depth and SwivelView orientation as the main window The following diagram shows an example of a PIP window within a main window and the registers used to position it Figure 13 1 Picture in Picture Plus with SwivelView disabled PIP window main window PIP window y start position panel s ori...

Page 150: ... in Picture Plus with SwivelView 180 enabled PIP window main window PIP window y start position panel s origin PIP window y end position PIP window x start position PIP window x end position 90 SwivelViewTM REG 8Dh REG 8Ch REG 85h REG 84h REG 89h REG 88h REG 91h REG 90h PIP window main window PIP window y start position panel s origin PIP window y end position PIP window x start position PIP windo...

Page 151: ... X31B A 001 08 13 2 3 SwivelView 270 Figure 13 4 Picture in Picture Plus with SwivelView 270 enabled PIP window main window PIP window y start position panel s origin PIP window y end position PIP window x start position PIP window x end position 270 SwivelViewTM REG 8Dh REG 8Ch REG 91h REG 90h REG 89h REG 88h REG 85h REG 84h ...

Page 152: ...omatically handled by byte swapping all read write data to from the internal display buffer and registers Bus data byte swapping translates all byte accesses correctly to the S1D13706 register and display buffer locations To maintain the correct translation for 16 bit word access even address bytes must be mapped to the MSB of the 16 bit word and odd address bytes to the LSB of the 16 bit word For...

Page 153: ...ta is stored at the odd system memory address location Bus data byte swapping automatic when the S1D13706 is configured for Big Endian causes the 16 bit pixel data to be stored byte swapped in the S1D13706 display buffer During display refresh this stored data must be byte swapped again before it is sent to the display aabb ccdd bb bb aa aa 0 15 0 15 D 15 8 D 7 0 MSB is assumed to be associated wi...

Page 154: ... but not the display data For 1 2 4 8 bpp color depth the Display Data Byte Swap bit REG 71h bit 6 must be set to 0 Figure 14 2 Byte swapping for 1 2 4 8 Bpp 11 22 22 22 11 11 0 15 0 15 D 15 8 D 7 0 High byte lane D 15 8 data e g 11 is associated with even address Low byte lane D 7 0 data e g 22 is associated with odd address CPU Data Byte Swap System Memory Display Buffer Big Endian Little Endian...

Page 155: ... mode because the S1D13706 dynamically enables the memory controller for display buffer writes 2 GPIO Pins are configured using the configuration pin CNF3 which is latched on the rising edge of RESET For information on CNF3 see Table 4 8 Summary of Power On Reset Options on page 29 3 GPIOs can be accessed and if configured as outputs can be changed After reset the S1D13706 is always in Power Save ...

Page 156: ...ion X31B A 001 08 Issue Date 01 11 13 16 Mechanical Data Figure 16 1 Mechanical Data 100pin TQFP15 S1D13706F00A All dimensions in mm 100 pin TQFP15 surface mount package 1 25 75 51 50 26 76 100 Index 0 10 14 0 0 1 14 0 0 1 16 0 0 4 16 0 0 4 0 5 0 18 1 0 0 1 0 125 0 5 0 2 1 0 1 0 05 0 1 0 05 0 025 1 3 max ...

Page 157: ...31B A 001 08 Figure 16 2 Mechanical Data 104pin CFLGA S1D13706B00A All dimensions in mm 104 pin CFLGA package 6 55 0 10 8 00 0 15 0 725 8 00 0 15 5 88 0 10 1 06 1 00max 0 05max 0 05max TOP VIEW L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 0 65 0 75 0 2 6 50 6 50 0 75 0 2 0 325 0 325 4 1 05 0 40 0 10 BOTTOM VIEW 0 15 M SIDE VIEW ...

Page 158: ...gramming Notes And Examples X31B G 003 xx S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 xx Interfacing to the PC Card Bus X31B G 005 xx S1D13706 Power Consumption X31B G 006 xx Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 xx Interfacing to the NEC VR4181 Microprocessor X31B G 008 xx Interfacing to the Motorola MPC821 Microprocessor X31B G 009 xx Interfacing to the...

Page 159: ... Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Mun...

Page 160: ...Page 154 Epson Research and Development Vancouver Design Center S1D13706 Hardware Functional Specification X31B A 001 08 Issue Date 01 11 13 THIS PAGE LEFT BLANK ...

Page 161: ...t but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Co...

Page 162: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 163: ...6 Bpp 65536 Colors 64 Gray Shades 16 4 Look Up Table LUT 17 4 1 Registers 17 4 1 1 Look Up Table Write Registers 17 4 1 2 Look Up Table Read Registers 18 4 2 Look Up Table Organization 19 4 2 1 Gray Shade Modes 20 4 2 2 Color Modes 22 5 Power Save Mode 26 5 1 Overview 26 5 2 Registers 27 5 2 1 Power Save Mode Enable 27 5 2 2 Memory Controller Power Save Status 27 5 3 Enabling Power Save Mode 28 5 ...

Page 164: ...elView 90 and 270 60 9 Identifying the S1D13706 61 10 Hardware Abstraction Layer HAL 62 10 1 API for 13706HAL 62 10 2 Initialization 65 10 2 1 General HAL Support 68 10 2 2 Advance HAL Functions 75 10 2 3 Surface Support 76 10 2 4 Register Access 80 10 2 5 Memory Access 82 10 2 6 Color Manipulation 84 10 2 7 Virtual Display 87 10 2 8 Drawing 89 10 2 9 Register Display Memory 95 10 3 Porting LIBSE ...

Page 165: ...Values for 4 Bpp Gray Shade 21 Table 4 5 Suggested LUT Values for 1 bpp Color 22 Table 4 6 Suggested LUT Values for 2 bpp Color 22 Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette 23 Table 4 8 Suggested LUT Values to Simulate VGA Default 256 Color Palette 24 Table 7 1 SwivelView Enable Bits 32 Table 8 1 32 bit Address Increments for Color Depth 41 Table 8 2 32 bit Address In...

Page 166: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 167: ...isplay Buffer 15 Figure 3 4 Pixel Storage for 8 Bpp in One Byte of Display Buffer 16 Figure 3 5 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer 16 Figure 8 1 Picture in Picture Plus with SwivelView disabled 37 Figure 8 2 Picture in Picture Plus with SwivelView disabled 48 Figure 8 3 Picture in Picture Plus with SwivelView 90 enabled 51 Figure 8 4 Picture in Picture Plus with SwivelView 180...

Page 168: ...Page 8 Epson Research and Development Vancouver Design Center S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 169: ... example source code referenced in this guide is available on the web at www eea epson com or www erd epson com This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13706 Most SED135x and SED137x products have HAL support thus allowing OEMs to do multiple designs with a common code base This document will be updated as appropriate Pl...

Page 170: ... chip For example the S5U13706 Evaluation Board uses a Cypress clock chip 3 Set all registers to initial values Table 2 1 Example Register Values contains the correct values for an example panel discussed below 4 Program the Look Up Table LUT with color values For details on programming the LUT see Section 4 Look Up Table LUT on page 17 5 Power up the LCD panel For details on powering up the LCD p...

Page 171: ...source 8 and the PCLK source CLKI2 Panel Setting Configuration 10h D0 1101 0000 Selects the following panel data format 2 color mono panel color panel data width 8 bit active panel resolution don t care panel type STN 11h 00 0000 0000 MOD rate don t care 12h 2B 0010 1011 Sets the horizontal total 14h 27 0010 0111 Sets the horizontal display period 16h 17h 00 00 0000 0000 0000 0000 Sets the horizon...

Page 172: ... 0000 Sets the sub window display start address 80h 81h 50 00 0101 0000 0000 0000 Sets the sub window line address offset 84h 85h 00 00 0000 0000 0000 0000 Sets the sub window X start position 88h 89h 00 00 0000 0000 0000 0000 Sets the sub window Y start position 8Ch 8Dh 4F 00 0100 1111 0000 0000 Sets the sub window X end position 90h 91h EF 00 1110 1111 0000 0000 Sets the sub window Y end positio...

Page 173: ...iguration B0h 00 0000 0000 Selects the following PWMOUT pin is software controlled PWM Clock circuitry is disabled CVOUT pin is software controlled CV Pulse circuitry is disabled B1h 00 0000 0000 Sets the PWM Clock and CV Pulse divides For this example the divides are not required B2h 00 0000 0000 Sets the CV Pulse Burst Length For this example the burst length is not required B3h 00 0000 0000 Set...

Page 174: ...o the S1D13706 display buffer varies with each individual hardware platform For further information on the display buffer see the S1D13706 Hardware Functional Specification document number X31B A 001 xx For further information on the S1D13706 Evaluation Board see the S5U13706B00C Evaluation Board Rev 1 0 User Manual document number X31B G 004 xx 3 2 Memory Organization for One Bit per pixel 2 Colo...

Page 175: ...re derived by indexing into the first 4 positions of the LUT 3 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades Figure 3 3 Pixel Storage for 4 Bpp in One Byte of Display Buffer At a color depth of 4 bpp each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting t...

Page 176: ...used to determine the gray shade intensity The green indices with six bits can resolve 64 gray shades 3 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades Figure 3 5 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer At a color depth of 16 bpp the S1D13706 is capable of displaying 64K 65536 colors The 64K color pixel is divided into three parts five bits for red six bits for green a...

Page 177: ...e pixel value indexes into the green component of the LUT and the amount of green at that index controls the intensity Monochrome mode look ups are done based on the Color Mono Panel Select bit REG 10h bit 6 4 1 Registers 4 1 1 Look Up Table Write Registers These registers contain the data to be written to the blue green red components of the Look Up Table The data is stored in these registers unt...

Page 178: ...ite only register and returns 00h if read Note For further information on the S1D13706 LUT architecture see the S1D13706 Hard ware Functional Specification document number X31B A 001 xx REG 0Bh Look Up Table Write Address Register LUT Write Address Bit 7 LUT Write Address Bit 6 LUT Write Address Bit 5 LUT Write Address Bit 4 LUT Write Address Bit 3 LUT Write Address Bit 2 LUT Write Address Bit 1 L...

Page 179: ...e between 0 and 0Fh The S1D13706 Look Up Table is linear This means increasing the LUT entry number results in a lighter color or gray shade For example a LUT entry of 0Fh in the red bank results in bright red output while a LUT entry of 05h results in dull red Table 4 1 Look Up Table Configurations Color Depth Look Up Table Indices Used Effective Gray Shades Colors RED GREEN BLUE 1 bpp gray 2 2 g...

Page 180: ...e The 1 bpp gray shade mode uses the green component of the first 2 LUT entries The remaining indices of the LUT are unused 2 bpp gray shade The 2 bpp gray shade mode uses the green component of the first 4 LUT entries The remaining indices of the LUT are unused Table 4 2 Suggested LUT Values for 1 Bpp Gray Shade Index Red Green Blue 00 00 00 00 01 00 FC 00 02 00 00 00 00 00 00 FF 00 00 00 Unused ...

Page 181: ... 64 intensities 6 bits 16 bpp gray shade The Look Up Table is bypassed at this color depth therefore programming the LUT is not required As with 8 bpp there are limitations to the colors which can be displayed In this mode the six bits of green are used to set the absolute intensity of the image This results in 64 gray shades Table 4 4 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue...

Page 182: ...ch byte in the display buffer contains eight adjacent pixels 2 bpp color When the S1D13706 is configured for 2 bpp color mode the first 4 entries in the LUT are used Each byte in the display buffer contains four adjacent pixels Table 4 5 Suggested LUT Values for 1 bpp Color Index Red Green Blue 00 00 00 00 01 FC FC FC 02 00 00 00 00 00 00 FF 00 00 00 Indicates unused entries in the LUT Table 4 6 S...

Page 183: ...er and lower nibbles of the byte are used as indices into the LUT The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 4 7 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 80 00 00 02 00 80 00 03 80 80 00 04 00 00 80 05 80 00 80 06 00 80 80 07 C0 C0 C0 08 80 80 80 09 FC 00 00 0A 00 FC 00 0B FC FC 00 0C 0...

Page 184: ...70 88 70 30 30 C8 20 20 40 09 50 50 F0 49 70 F0 90 89 70 40 30 C9 20 20 40 0A 50 F0 50 4A 70 F0 B0 8A 70 50 30 CA 30 20 40 0B 50 F0 F0 4B 70 F0 D0 8B 70 60 30 CB 30 20 40 0C F0 50 50 4C 70 F0 F0 8C 70 70 30 CC 40 20 40 0D F0 50 F0 4D 70 D0 F0 8D 60 70 30 CD 40 20 30 0E F0 F0 50 4E 70 B0 F0 8E 50 70 30 CE 40 20 30 0F F0 F0 F0 4F 70 90 F0 8F 40 70 30 CF 40 20 20 10 00 00 00 50 B0 B0 F0 90 30 70 30 D...

Page 185: ...00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 F0 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 F0 00 70 70 00 00 B0 00 00 40 F0 20 40 20 31 00 F0 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 F0 70 72 70 30 00 B2 20 00 40 F2 20 40 30 33 00 F0 B0 73 70 50 00 B3 30 00 40 F3 20 40 30 34 00 F0 F0 74 70 70 00 B4 40 00 40 F4 20 40 40 35 00 B0 F0 75 50 70 00 B5 40 00 30 F5 20 30 40 36 00 70 F0 76 30 70 00 B...

Page 186: ... ensure the LCD bias power supply is disabled properly For further information on LCD power sequencing see Section 6 LCD Power Sequencing on page 29 For Power Save Mode AC Timing see the S1D13706 Hardware Functional Specification document number X31B A 001 xx 5 1 Overview The S1D13706 includes a software initiated Power Save Mode Enabling disabling Power Save Mode is controlled using the Power Sav...

Page 187: ...ave Status The Memory Controller Power Save Status bit is a read only status bit which indicates the power save state of the S1D13706 SRAM interface When this bit returns a 1 the SRAM interface is powered down When this bit returns a 0 the SRAM interface is active This bit returns a 0 after a chip reset Note The memory clock source may be disabled when this bit returns a 1 REG A0h Power Save Confi...

Page 188: ...ock source may be disabled Optional 5 Optionally when the Memory Controller Power Save Status bit REG A0h bit 3 returns a 1 the Memory Clock source may be safely shut down 5 4 Disabling Power Save Mode Power Save Mode must be disabled using the following steps 1 If the Memory Clock source is shut down it must be started and the Memory Control ler Power Save Status bit must return a 0 Note if the p...

Page 189: ...the LCD This time interval depends on the LCD bias power supply design For example the LCD bias power supply on the S5U13706 Evaluation board requires 0 5 seconds to fully discharge Other power supply designs may vary This section assumes the LCD bias power is controlled through GPO The S1D13706 GPIO pins are multi use pins and may not be available in all system designs For further infor mation on...

Page 190: ...o activate the LCD bias power Note seLcdDisplayEnable is included in the C source file hal_misc c available on the internet at www eea epson com 6 2 Disabling the LCD Panel The HAL function seDisplayEnable FALSE can be used to disable the LCD panel The function disables the LCD panel using the following steps 1 Disable the LCD power using GPO 2 Wait for the LCD bias power supply to discharge based...

Page 191: ...ng in a display that is higher than it is wide Rotating the image on a 320x240 display by 90 or 270 degrees yields a display that is now 240 pixels wide and 320 pixels high SwivelView also works with panels that are designed with a portrait orientation In this case when SwivelView 0 is selected the panel will be in a portrait orientation A selection of SwivelView 90 or SwivelView 270 rotates to a ...

Page 192: ...eight refer to the physical panel dimensions Note Truncate all fractional values before writing to the address registers In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address panel height bpp 8 4 1 REG 71h Special Effects Register Display Data Word Swap Display Data Byte Swap n a Sub Window Enable n a n a SwivelView Mode Se...

Page 193: ...set to values which are greater than that required for the given display width These registers indicate the number of dwords per line in the main window image typically the panel width number of dwords per line image width 32 bpp Note The image width must be a multiple of 32 bpp If the panel width is not such a multi ple a slightly larger width is chosen Note Round up to the nearest integer all li...

Page 194: ...s Offset registers REG 78h is set to 28h and REG 79h is set to 00h Example 2 In SwivelView 90 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Confirm the main window coordinates are valid The vertical coordinates must be a multiple of 32 bpp 240 32 4 30 Main window vertical coordinate is valid 2 Determine the main window display start address The main window ...

Page 195: ...laced at the start of display memory which is at display address 0 main window display start address register desired byte address panel width panel height bpp 8 4 1 0 320 240 4 8 4 1 9599 257Fh Program the Main Window Display Start Address registers REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h 3 Determine the main window line address offset number of dwords per line image...

Page 196: ... 180 In SwivelView 0 and 180 the main window line address offset register requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the main window line address offset register must be programmed to a longer line which is a multiple of 32 bits per pixel This longer line creates a virtual image where the width is main window line address offset register 32 bits per...

Page 197: ...us with SwivelView disabled 8 2 Registers These are registers which control the Picture In Picture Plus feature This bit enables a sub window within the main window The location of the sub window within the landscape window is determined by the Sub Window X Position registers REG 84h REG 85h REG 8Ch REG 8Dh and Sub Window Y Position registers REG 88h REG 89h REG 90h REG 91h The sub window has its ...

Page 198: ...View 180 program the start address desired byte address panel width panel height bpp 8 4 1 In SwivelView 270 program the start address desired byte address panel width 1 panel height bpp 8 4 Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the panel height to be a multiple of 32 bits per pix el If this is not possible a virtual d...

Page 199: ...e address is the starting display address for the sub window image and panel width and panel height refer to the physical panel dimensions Width and height are used respective to the given SwivelView mode For example the sub window height in SwivelView 90 is the sub window width in SwivelView 180 In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start ad...

Page 200: ... height to be a multiple of 32 bpp If this is not possible a virtual display one larger than the physical panel size is required which does satisfy the above requirements To create a virtual display program the sub win dow line address offset to values which are greater than that required for the given dis play width These registers indicate the number of dwords per line in the sub window image nu...

Page 201: ...ne increments In SwivelView 0 these registers set the horizontal coordinates x of the sub windows s top left corner Increasing values of x move the top left corner towards the right in steps of 32 bits per pixel see Table 8 1 Program the Sub Window X Start Position registers so that sub window X start position registers x 32 bits per pixel Note x must be a multiple of 32 bits per pixel In SwivelVi...

Page 202: ... position registers panel width y These bits determine the Y start position of the sub window in relation to the origin of the panel Due to the S1D13706 SwivelView feature the Y start position may not be a vertical position value only true in 0 and 180 SwivelView For further information on defining the value of the Y Start Position registers see Section 8 3 Picture In Picture Plus Examples on page...

Page 203: ...ow Y Start Position registers so that sub window Y start position registers panel height x 32 bits per pixel Note panel height x must be a multiple of 32 bits per pixel In SwivelView 180 these registers set the vertical coordinates y of the sub window s bottom right corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y Start Position regis...

Page 204: ...ments In SwivelView 0 these registers set the horizontal coordinates x of the sub windows s bottom right corner Increasing values of x move the bottom right corner towards the right in steps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bits per pixel In SwivelView...

Page 205: ...teps of 32 bits per pixel see Table 8 3 Program the Sub Window X End Position registers so that sub window X end position registers panel width x 32 bits per pixel 1 Note panel width x must be a multiple of 32 bits per pixel In SwivelView 270 these registers set the vertical coordinates y of the sub window s top right corner Increasing values of y move the top right corner downwards in steps of 1 ...

Page 206: ...corner Increasing values of y move the bottom right corner downwards in steps of 1 line Program the Sub Window Y End Position registers so that sub window Y end position registers y 1 In SwivelView 90 these registers set the horizontal coordinates x of the sub window s bottom left corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 ...

Page 207: ...position registers panel height y 1 In SwivelView 270 these registers set the horizontal coordinates x of the sub window s top right corner Increasing values of x move the top right corner towards the right in steps of 32 bits per pixel see Table 8 4 Program the Sub Window Y End Position registers so that sub window Y end position registers x 32 bits per pixel 1 Note x must be a multiple of 32 bit...

Page 208: ...ame image for both the main window and sub window To do so set the sub window line address offset registers to the same value as the main win dow line address offset registers Example 5 Program the main window and sub window registers for a 320x240 pan el at 4 bpp with the sub window positioned at 80 60 with a width of 160 and a height of 120 1 Confirm the main window coordinates are valid The hor...

Page 209: ...ne address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h 5 Determine the sub window display start address The main window image must take up 320 x 240 pixels 2 pixels per byte 9600h bytes If the main window starts at address 0h the sub window can start at 9600h sub window dis...

Page 210: ...inates of the sub window s top left and bottom right corners Program the Y Start Position registers y1 Program the Y End Position registers y2 1 X Start Position registers 80 32 4 10 0Ah Y Start Position registers 60 3Ch X End Position registers 80 160 32 4 1 29 1Dh Y End Position registers 60 120 1 179 B3h Program the Sub window X Start Position register REG 84h is set to 0Ah and REG 85h is set t...

Page 211: ...me value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the SwivelView 0 orientation In SwivelView 90 these registers switch their functionality as described in Section 8 2 Registers Example 6 In SwivelView 90 pro...

Page 212: ... 8 4 1 0 240 4 8 4 1 29 1Dh Program the Main Window Display Start Address registers REG 74h is set to 1Dh REG 75h is set to 00h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset register REG 78h is set to 1Eh and REG 79h is set to 00h 5 Determine the sub window display s...

Page 213: ...the horizontal coordinates of the sub window top right and bottom left corner Program the Y Start Position registers panel height x2 32 bpp Program the Y End Position registers panel height x1 32 bpp 1 X Start Position registers 80 50h Y Start Position registers 240 64 120 32 4 07h X End Position registers 80 160 1 239 EFh Y End Position registers 240 64 32 4 1 21 15h Program the Sub window X Star...

Page 214: ... value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the SwivelView 0 orientation In SwivelView 180 these registers switch their functionality as described in Section 8 2 Registers Example 7 In SwivelView 180 pro...

Page 215: ...9599 257Fh Program the Main Window Display Start Address registers REG 74h is set to 7Fh REG 75h is set to 25h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset registers REG 78h is set to 28h and REG 79h is set to 00h 5 Determine the sub window display start address The...

Page 216: ... registers panel width x1 32 bpp 1 The Y position registers set the horizontal coordinates of the sub window bottom right and top left corner Program the Y Start Position registers panel height y2 Pro gram the Y End Position registers panel height y1 1 X start position registers 320 80 160 32 4 10 0Ah Y start position registers 240 60 120 60 3Ch X end position registers 320 80 32 4 1 29 1Dh Y end ...

Page 217: ... same value as the main win dow line address offset registers Note The Sub Window X Start Position registers Sub Window Y Start Position registers Sub Window X End Position registers and Sub Window Y End Position registers are named according to the SwivelView 0 orientation In SwivelView 270 these registers switch their functionality as described in Section 8 2 Registers Example 8 In SwivelView 27...

Page 218: ...address panel width 1 panel height bpp 8 4 0 320 1 240 4 8 4 9570 2562h Program the Main Window Display Start Address registers REG 74h is set to 62h REG 75h is set to 25h and REG 76h is set to 00h 4 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset registers REG 78h is set to 1Eh and REG 79h is se...

Page 219: ...sition registers panel width y1 1 The Y position registers sets the horizontal coordinates of the sub window top right and bottom left corner Program the Y Start Position registers x1 32 bpp Pro gram the Y End Position registers x2 32 bpp 1 X start position registers 320 80 160 80 50h Y start position registers 64 32 4 08h X end position registers 320 80 1 239 EFh Y end position registers 64 120 3...

Page 220: ...ine creates a virtual image whose width is sub window line address offset register 32 bits per pixel and the sub window image must be drawn right justified to this virtual width 8 4 2 SwivelView 90 and 270 In SwivelView 90 and 270 the main window line address offset register requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the main window line address of...

Page 221: ...g the S1D13706 The S1D13706 can be identified by reading the value contained in the Revision Code Register REG 00h To identify the S1D13706 follow the steps below 1 Read REG 00h 2 The production version of the S1D13706 returns a value of 28h 00101000b 3 The product code is Ah 001010b based on bits 7 2 4 The revision code is 0h 00b based on bits 1 0 ...

Page 222: ...he HAL seRegisterDevice MUST be the first HAL function called by an application seInitReg Initializes the registers LUT and allocates memory for default surfaces seGetHalVersion Returns HAL library version information seHalTerminate Frees up memory allocated by the HAL before the application exits seGetId Identifies the controller by interpreting the revision code register General HAL Support seGe...

Page 223: ... from the start of display buffer to the start of surface memory seAllocMainWinSurface seAllocSubWinSurface Manually allocates display buffer memory for a surface seFreeSurface Frees any allocated surface memory seSetMainWinAsActiveSurface seSetSubWinAsActiveSurface Changes the active surface sePwmEnable Enables the PWMCLK circuitry seCvEnable Enables the CV Pulse circuitry sePwmControl Configures...

Page 224: ...display device over the indicated virtual surface Drawing seSetPixel seSetMainWinPixel seSetSubWinPixel Set one pixel at the specified x y co ordinate and color seGetPixel seGetMainWinPixel seGetSubWinPixel Returns the color of the pixel at the specified x y co ordinate seDrawLine seDrawMainWinLine seDrawSubWinLine Draws a line between two endpoints in the specified color seDrawRect seDrawMainWinR...

Page 225: ...ointed to by lpHalInfo Additionally this routine allocates system memory as address space for accessing registers and the display buffer Parameters lpHalInfo A pointer to a HAL_STRUCT structure This structure must be filled with appropriate values prior to calling seRegisterDevice Return Value ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE The HAL was unable to locate the S1D13706 ...

Page 226: ...t in table ERR_CLKI2_NOT_IN_TABLE Could not program CLKI2 in clock synthesizer because selected frequency not in table void seGetHalVersion const char pVersion const char pStatus const char pRevision Description Retrieves the HAL library version information By retrieving and displaying the HAL ver sion information along with application version information it is possible to determine at a glance w...

Page 227: ...ld not find PCI driver Intel Windows platform only ERR_PCI_BRIDGE_ADAPTER_NOT_FOUND Could not find PCI Bridge Adapter board Intel Windows platform only ERR_FAILED Could not free memory int seGetId int pId Description Reads the S1D13706 revision code register to determine the controller product and revi sion Parameters pId A pointer to an integer to receive the controller ID The value returned is t...

Page 228: ... is the size of the available amount of display buffer memory directly accessible to an application int seEnableHardwareDisplaySwapping int Enable Description The S1D13706 requires 16 bits per pixel data to be in little endian format On big endian systems the software or hardware needs to swap this data seEnableHardwareDisplay Swapping is intended to be used on big endian systems where system perf...

Page 229: ... orientation Parameters Width A pointer to an unsigned integer which will receive the width in pixels for the indicated surface Height A pointer to an unsigned integer which will receive the height in pixels for the indicated surface Return Value seGetResolution returns one of the following ERR_OK Function completed successfully ERR_FAILED Returned when there is not an active display surface seGet...

Page 230: ...each line of the displayed image Note that the displayed image may be larger than the physical size of the LCD seGetBytesPerScanline returns the number of bytes per scanline for the current active surface seGetMainWinBytesPerScanline and seGetSubWinBytesPerScanline return the num ber of bytes per scanline for the surface indicated in the function name To work correctly these routines require the S...

Page 231: ...erSaveMode returns the current state of power save mode Parameters None Return Value The return value is TRUE if power save mode is enabled The return value is FALSE if power save mode is not enabled void seSetPowerUpDelay WORD PowerupTime Description seSetPowerUpDelay sets the power up delay for seSetPowerSaveMode Parameters PowerupTime Power up time in milliseconds Return Value None void seSetPo...

Page 232: ...LCD display The SwivelView status is read directly from the S1D13706 registers Calling this function when the LCD display is not initialized will result in an erroneous return value Note seGetSwivelViewMode was previously called seGetLcdOrientation It is now rec ommended to call seGetSwivelViewMode instead of seGetLcdOrientation Parameters None Return Value LANDSCAPE Not rotated ROTATE90 Display i...

Page 233: ...ons to delay the desired amount of time using the system clock Parameters Seconds The number of seconds to delay for Return Value ERR_OK Returned by all platforms at the completion of a successful delay ERR_FAILED Returned by non Intel platforms in which the power save mode is enabled void seDisplayBlank BOOL Blank void seMainWinDisplayBlank BOOL Blank void seSubWinDisplayBlank BOOL Blank Descript...

Page 234: ...able or disable the selected display device seDisplayEnable enables or disables the display for the active surface seMainWinDisplayEnable enables or disables the main window display for the S1D13706 the display blank feature is used to enable or disable the main window seSubWinDisplayEnable enables or disables the sub window display Parameters Enable Call with Enable set to TRUE to enable the disp...

Page 235: ...of latency for programs running on a Windows platform Note The application should not leave it s thread running in a high priority state for long peri ods of time As soon as a time critical operation is complete the application should call seEndHighPriorty Parameters None Return Value The priority nest count which is the number of times seBeginHighPriority has been called without a corresponding c...

Page 236: ...MHz FREQ_25000 25 000 MHz FREQ_25175 25 175 MHz FREQ_28318 28 318 MHz FREQ_30000 30 000 MHz FREQ_31500 31 500 MHz FREQ_32000 32 000 MHz FREQ_33000 33 000 MHz FREQ_33333 33 333 MHz FREQ_34000 34 000 MHz FREQ_35000 35 000 MHz FREQ_36000 36 000 MHz FREQ_40000 40 000 MHz FREQ_49500 49 500 MHz FREQ_50000 50 000 MHz FREQ_56250 56 250 MHz FREQ_65000 65 000 MHz FREQ_80000 80 000 MHz FREQ_100000 100 000 MH...

Page 237: ...e 0 if this function is called before initializing the registers DWORD seGetSurfaceLinearAddress void Description This function returns the linear address of the start of memory for the active surface Parameters None Return Value The return value is the linear address to the start of memory for the active surface A linear address is a 32 bit offset in CPU address space The return value will be NUL...

Page 238: ...led Parameters Size The size in bytes of the requested memory block Return Value If the memory allocation succeeds then the return value is the linear address of the allo cated memory If the allocation fails then the return value is 0 A linear address is a 32 bit offset in CPU address space int seFreeSurface DWORD LinearAddress Description This function can be called to free any previously allocat...

Page 239: ...ECT ClkSource int ClkDivide int DutyCycle Description This function sets up the Pulse Width Modulation PWM clock configuration registers Parameters ClkSource The clock source for PWM set to either CLKI or CLKI2 ClkDivide The clock source is divided by 2 ClkDivide Legal values for ClkDivide are from 0 to 12 decimal For example if ClkDivide is 3 the clock source is divided by 2 3 8 DutyCycle The PWM...

Page 240: ...wap bytes if the endian of the host CPU differs from the S1D13706 the S1D13706 is little endian unsigned seReadRegByte DWORD Index Description This routine reads the register specified by Index and returns the value Parameters Index Offset in bytes to the register to read Return Value The least significant byte of the return value is the byte read from the register unsigned seReadRegWord DWORD Ind...

Page 241: ...o the specified index Parameters Index Offset to the register pair to be written Value The value in the least significant word to write to the registers Return Value None void seWriteRegDword DWORD Index DWORD Value Description This routine writes the value specified to four registers starting at Index Parameters Index Offset to the first of four registers to be written to Value The dword value to...

Page 242: ...a byte from the display buffer memory at the specified offset and returns the value Parameters Offset Offset in bytes from start of the display buffer to the byte to read Return Value The return value in the least significant byte is the byte read from display memory unsigned seReadDisplayWord DWORD Offset Description Reads one word from display buffer memory at the specified offset and returns th...

Page 243: ...st word to write Value An unsigned integer containing the word to written in the least significant word Count Number of words to write All words will have the same value Return Value None void seWriteDisplayDwords DWORD Offset DWORD Value DWORD Count Description This routine writes one or more dwords to display memory starting at the specified offset Parameters Offset Offset in bytes from the star...

Page 244: ...Value None void seReadLutEntry int Index BYTE pRGB Description seReadLutEntry reads one lookup table entry and returns the results in the byte array pointed to by pRGB Parameter Index Offset to the lookup table entry to be read i e setting index to 2 returns the value of the third RGB element of the lookup table pRGB A pointer to an array to receive the lookup table data The array must be at least...

Page 245: ...PerPixel It is now recommended to call seSetMode instead of seSetBitsPerPixel In addition hardware display swapping is enabled or disabled based on the requirements described in seEnableHardwareDisplay Swapping IMPORTANT When the LCD color depth is changed memory allocated for both the main window and sub window display buffer is freed and the display buffer memory is reassigned The application mu...

Page 246: ...xamples X31B G 003 03 Issue Date 01 02 23 Parameters None Return Value None unsigned seGetBitsPerPixel void Description seGetBitsPerPixel returns the current color depth for the associated display surface Parameters None Return Value The color depth of the surface This value will be 1 2 4 8 or 16 ...

Page 247: ...ates one block of memory for both the main window and sub window based on width and height and color depth Memory previously allocated for the given display surface is released then reallocated to the larger size Note The width programmed may be larger than that requested in the respective function ar gument This is to ensure that the value programmed into the address offset registers is a multipl...

Page 248: ... image the display is treated as a window into the virtual image These functions allow an application to pan right and left and scroll up and down the display over the virtual image seVirtPanScroll will pan and scroll the current active surface seMainWinVirtPanScroll and seSubWinVirtPanScroll will pan and scroll the surface indicated in the function name seMainAndSubWinVirtPanScroll will pan and s...

Page 249: ...d color Use seSetPixel to set one pixel on the current active surface See seSetMainWinAsAc tiveSurface and seSetSubWinAsActiveSurface for information about changing the active surface Use seSetMainWinPixel and seSetSubWinPixel to set one pixel on the surface indi cated in the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameter...

Page 250: ...n the display surface referenced in the function name Parameters x The X co ordinate in pixels of the pixel to read y The Y co ordinate in pixels of the pixel to read Return Value The return value is a dword describing the color read at the x y co ordinate Color is interpreted differently at different color depths If no memory was allocated to the surface the return value is DWORD 1 At 1 2 4 and 8...

Page 251: ...e If no memory was allocated to the surface these functions return without writing to dis play memory Parameters x1 The X co ordinate in pixels of the first endpoint of the line to be drawn y1 The Y co ordinate in pixels of the first endpoint of the line to be drawn x2 The X co ordinate in pixels of the second endpoint of the line to be drawn y2 The Y co ordinate in pixels of the second endpoint o...

Page 252: ...rectangle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters x1 The X co ordinate in pixels of the upper left corner of the rectangle y1 The Y co ordinate in pixels of the upper left corner of the rectangle x2 The X co ordinate in pixels of the lower right corner of the rectangle y2 Th...

Page 253: ...nAsActiveSurface for information about changing the active surface Use seDrawMainWinCircle and seDrawSubWinCircle draw the circle on the display surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters x The X co ordinate in pixels of the center of the circle y The Y co ordinate in pixels of the center of ...

Page 254: ... changing the active surface Use seDrawMainWinEllipse and seDrawSubWinEllipse to draw the ellipse on the dis play surface indicated by the function name If no memory was allocated to the surface these functions return without writing to dis play memory Parameters xc The X co ordinate in pixels of the center of the ellipse yc The Y co ordinate in pixels of the center of the ellipse xr A long intege...

Page 255: ...functions are provided DWORD seGetLinearDisplayAddress void Description This function returns the linear address for the start of physical display memory Parameters None Return Value The return value is the linear address of the start of display memory A linear address is a 32 bit offset in CPU address space DWORD seGetLinearRegAddress void Description This function returns the linear address of t...

Page 256: ...e that sets up the chip selects or interrupts etc What if you wanted to build the application for an SH 3 target one not running windows Before you can build that application to load onto the target you need to build a C library for the target that contains enough of the target specific code like putch and getch to let you build the application Epson supplies the LIBSE for this purpose but your co...

Page 257: ...ome board configuration board communications and assigning memory blocks with chip selects and a jump into the applications main function In the embedded targets putch xxxputch c and getch xxxgetch c resolve to serial character input output For SH3 much of the detail of handling serial IO is hidden in the monitor of the evaluation board but in general the primitives are fairly straight forward pro...

Page 258: ...ancouver Design Center S1D13706 Programming Notes and Examples X31B G 003 03 Issue Date 01 02 23 11 Sample Code Example source code demonstrating programming the S1D13706 using the HAL library is available on the internet at www eea epson com ...

Page 259: ... REG 1Fh VERTICAL DISPLAY PERIOD START POSITION REGISTER 1 RW n a n a n a n a n a n a Vertical Display Period Start Position bit 9 bit 8 REG 20h FPLINE PULSE WIDTH REGISTER RW FPLINE Pulse Polarity FPLINE Pulse Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 22h FPLINE PULSE START POSITION REGISTER 0 RW FPLINE Pulse Start Position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 23h FPLINE ...

Page 260: ...erved Reserved Reserved Reserved REG ACh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 0 RW n a GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status GPIO0 Pin IO Status REG ADh GENERAL PURPOSE IO PINS STATUS CONTROL REGISTER 1 RW GPO Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved REG B0h PWM CLOCK CV PULSE...

Page 261: ...luating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ar...

Page 262: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 THIS PAGE LEFT BLANK ...

Page 263: ...tents 13706CFG 5 S1D13706 Supported Evaluation Platforms 5 Installation 6 Usage 6 13706CFG Configuration Tabs 7 General Tab 7 Preferences Tab 9 Clocks Tab 10 Panel Tab 14 Panel Power Tab 18 Registers Tab 19 13706CFG Menus 20 Open 20 Save 21 Save As 21 Configure Multiple 22 Export 23 Enable Tooltips 24 ERD on the Web 24 About 13706CFG 24 Comments 24 ...

Page 264: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 13706CFG Configuration Program X31B B 001 03 Issue Date 01 03 29 THIS PAGE LEFT BLANK ...

Page 265: ...y the configuration information can be saved in a variety of text file formats for use in other applications S1D13706 Supported Evaluation Platforms 13706CFG runs on PC system running Windows 9x ME NT 2000 and can modify the executable files for the following evaluation platforms PC system with an Intel 80x86 processor M68EC000IDP Integrated Development Platform board revision 3 0 with a Motorola ...

Page 266: ...llation To start 13706CFG from a Windows command prompt change to the directory 13706cfg exe was installed to and type the command 13706cfg The basic procedure for using 13706CFG is 1 Start 13706CFG as described above 2 Open an existing file to serve as a starting reference point this step is optional 3 Modify the configuration For specific information on editing the configuration see 13706CFG Con...

Page 267: ...aluation board specific information The values presented are used for configuring HAL based executable utilities The settings on this tab specify where in CPU address space the registers and display buffer are located Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation p...

Page 268: ...decimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected Note When Epson S5U13706B00B B00C Evaluation Board is selected the register and display buffer addresses are blanked because the evaluation board uses the PCI interface and the decode addresses are determined by the system BIOS during boot up If using the S1D13706 Evaluation B...

Page 269: ...rt the display data going to the LCD panel The display data is inverted after the Look Up Table S W Invert Enable The Video Invert feature can be controlled by software using REG 70h bit 4 When this box is checked the Software Video Invert bit is set to one and video data is inverted If the box is unchecked the bit is set to zero and video data remains normal H W Invert Enable The Video Invert fea...

Page 270: ...s for the input clocks are displayed in blue in the Auto section of each group It is the responsibility of the system designer to ensure that the correct CLKI frequencies are supplied to the S1D13706 Making a selection other than Auto indicates that the values for CLKI or CLKI2 are known and are fixed by the system design Options for LCD frame rates are limited to ranges determined by the clock va...

Page 271: ...frequency of CLKI2 Select Auto to have the CLKI2 frequency determined automatically based on settings made on other configu ration tabs After completing the other configurations the required CLKI2 frequency will be displayed in blue in the Auto section If the system design requires the CLKI2 frequency to be fixed at a particular rate set this value by selecting a preset frequency from the drop dow...

Page 272: ...ve BCLK Timing This field shows the actual BCLK frequency used by the configuration process MCLK These settings select the clock signal source and input clock divisor for the memory clock MCLK MCLK should be set as close to the maximum 50 MHz as possible Source The MCLK source is BCLK Divide Specifies the divide ratio for the clock source signal The divide ratio is applied to the MCLK source to de...

Page 273: ... shows the actual PWMCLK frequency used by the configuration process Duty Cycle Selects the number of cycles that PWMOUT is high out of 256 clock periods Contrast Voltage Pulse These controls configure various Contrast Voltage CV Pulse settings The CV Pulse is provided for panels which support the contrast voltage function Enable When this box is checked the CV Pulse circuitry is enabled Force Hig...

Page 274: ... Therefore confirm all settings on this tab after the Panel Type is changed Panel Data Width Selects the panel data width Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn t be confused with color depth which determines the number of displayed colors When the panel type is STN the available options are 4 8 and 16 bit When an active panel ty...

Page 275: ...e in the selection boxes If the width height of your panel is not listed enter the actual panel dimensions into the edit field For passive panels manually entered pixel widths must be a minimum of 32 pixels and can be increased by multiples of 16 For TFT panels manually entered pixel widths must be a minimum of 16 pixels and can be increased by multiples of 8 If a value is entered that does not ma...

Page 276: ...ocks tab For example If CLKI is chosen to be Auto and PCLK is sourced from CLKI on the Clocks tab then the range for Pixel Clock will range from 1 5 MHz to 80 MHz Selecting a fixed PCLK on the Clocks tab say 25 175 MHz will result in only four selections 6 293 8 392 12 587 and 25 175 MHz these frequencies represent the four possible frequencies from a fixed 25 175 MHz input clock divided by the PC...

Page 277: ...ion of the FPFRAME pulse settings Start pos Specify the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pulse Pulse width Specifies the pulse width in lines of the FPFRAME output signal Predefined Panels 13706CFG uses a file panels def which lists various panel manufacturers recommended settings If the file panels def is present in the same direc...

Page 278: ...ff and when the S1D13706 control signals are turned off This setting must be configured according to the specification for the panel being used This value is only used by Epson evaluation software designed for the S5U13706B00C evaluation board Power Up Time Delay This setting controls the time delay between when the S1D13706 control signals are turned on and the LCD panel is powered on This settin...

Page 279: ...anged by double clicking on the register in the listing Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the S1D13706 Hardware Functional Specification document number X31B A 001 xx be referred to before making an manual register settings Manually entered values may be changed by 13706CFG if furthe...

Page 280: ... to quickly arrive at a starting point for register configuration The only requirement is that the file being opened must contain a valid S1D13706 HAL library information block 13706CFG supports a variety of executable file formats Select the file type s 13706CFG should display in the Files of Type drop down list and then select the filename from the list and click on the Open button Note 13706CFG...

Page 281: ...13706cfg exe and config uring the copy It is not possible to configure the original while it is running Save As From the Menu Bar select File then Save As to display the Save As Dialog Box Save as is very similar to Save except a dialog box is displayed allowing the user to name the file before saving Using this technique a tester can configure a number of files differing only in configuration inf...

Page 282: ...ndows Explorer Selecting Show all files displays all files in the selected directory whereas selecting Show conf files only will display only files that can be configured using 13706CFG i e exe s9 elf The configuration values can be saved to a specific EXE file for Intel platforms or to a specific S9 or ELF file for non Intel platforms The file must have been compiled using the 13706 HAL library C...

Page 283: ...ystems such as Linux QNX and VxWorks UGL or WindML a comma delimited text file containing an offset a value and a description for each S1D13706 register After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configuration file clicking the Preview button starts Notepad with a copy of the co...

Page 284: ...ite About 13706CFG Selecting the About 13706CFG option from the Help menu displays the about dialog box for 13706CFG The about dialog box contains version information and the copyright notice for 13706CFG Comments On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13706 i e Selecting TFT or STN on the Panel tab enables disables o...

Page 285: ...S1D13706 Embedded Memory LCD Controller 13706SHOW Demonstration Program Document Number X31B B 002 03 ...

Page 286: ...n evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windo...

Page 287: ...t it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a ...

Page 288: ...utomatically b n Shows the LCD display at a user specified color depth bpp where n 1 2 4 8 16 g n Shows the image overlaid with a 20 pixel wide grid where n white 0 or black 1 If n is not specified the grid defaults to white noinit Skips full register initialization Only registers used for changing the color depth bpp are updated Additionally some registers are read to determine infor mation such ...

Page 289: ...re not supported at the customer level bigmem Assumes memory size is 2M bytes instead of 80K bytes for testing purposes only noclkerr Allows invalid SwivelView clock settings for testing purposes only read After drawing the image continually reads the entire display buffer in dword increments for testing purposes only write Continually writes to one word of offscreen memory for testing purposes on...

Page 290: ...ault color depth as selected by 13706CFG Each screen is shown for approximately 1 second before the next screen is automatically shown The program exits after the last screen is shown To exit the program immediately press CTRL BREAK 3 To show a color pattern for a specific color depth type the following 13706SHOW b mode where mode 1 2 4 8 or 16 The program displays the requested color depth and th...

Page 291: ...xits To exit the pro gram immediately press the Esc key The s switch can be used in combination with other command line switches Comments If 13706SHOW is started without specifying the color depth b the program automat ically cycles through the available color depths from highest to lowest The first color depth shown is the default color depth value saved to 13706SHOW using 13706CFG This approach ...

Page 292: ...Page 8 Epson Research and Development Vancouver Design Center S1D13706 13706SHOW Demonstration Program X31B B 002 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 293: ...ting Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are r...

Page 294: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 13706PLAY Diagnostic Utility X31B B 003 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 295: ...is software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program to send control commands and information to the target processor Alternatively the PC can program...

Page 296: ...le 13706play exe to a directory in the path e g PATH C S1D13706 Embedded platform Download the program 13706play to the system Usage PC platform At the prompt type 13706play Where displays copyright and program version information Embedded platform Execute 13706play and at the prompt type the command line argument Where displays copyright and program version information ...

Page 297: ...es for CLKI is displayed Where Displays a list of available frequencies for CLKI MHz iFreq Sets CLKI to an index representing a preset frequency MHz specified by iFreq iFreq is based on the table provided with the command CLKI Note The CLKI command programs preset frequencies available on the S5U13706B00C evaluation board This function is not designed for use on other evaluation platforms or proto...

Page 298: ...100t is 100 decimal FW addr1 addr2 data Fills a specified address range with 16 bit data words Where addr1 Start address of the range to be filled hex addr2 End address of the range to be filled hex data Data to be written hex Data can be a list of words to be repeated for the duration of the fill To use decimal values attach a t suffix to the value e g 100t is 100 decimal H lines Sets the number ...

Page 299: ...y bits 7 2 of each color are used in the LUT For example 04h is the first color in tensity after 00h Valid LUT colors follow the pattern 00h 04h FCh M bpp Sets the color depth bpp If no color depth is provided information about the current settings are listed Where bpp Color depth to be set 1 2 4 8 16 bpp Q Quits the program P on off Controls the power on off state of the S1D13706 Where on Powers ...

Page 300: ...ata can be a list of bytes to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b WD addr data Writes dword s of data to specified memory address Where addr Address data is written to data Data to be written hex Data can be a list of dwords to be repeated for the durati...

Page 301: ...at index If no data is specified reads the 32 bit dword data from the register at index Where index Index into the registers hex data Data to be written to read from register hex Data can be a list of dwords to be repeated for the duration of the write To use decimal values attach a t suffix to the value e g 100t is 100 decimal To use binary values attach a b suffix to the value e g 0111 b XW inde...

Page 302: ... 13706CFG User Manual document number X31B B 001 xx 2 Type 13706PLAY to start the program 3 Type for help 4 Type i to initialize the registers 5 Type xa to display the contents of the registers 6 Type x 34 to read register 34h 7 Type x 34 10 to write 10h to register 34h 8 Type f 0 ffff aa to fill the first FFFFh bytes of the display buffer with AAh 9 Type r 0 100 to read the first 100h bytes of th...

Page 303: ...regs scr results This causes the file dumpregs scr to be interpreted as commands by 13706PLAY and the results to be sent to the file results Example 1 Create a script file that reads all registers and then exits This file initializes the S1D13706 and reads the registers Note after a semicolon all characters on a line are ignored Note all script files must end with the q command Initialize the S1D1...

Page 304: ...Page 12 Epson Research and Development Vancouver Design Center S1D13706 13706PLAY Diagnostic Utility X31B B 003 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 305: ...ating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are ...

Page 306: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 13706BMP Demonstration Program X31B B 004 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 307: ...Windows 9x NT Other embedded platforms are not supported due to the possible lack of system memory or structured file system The 13706BMP demonstration utility must be configured and or compiled to work with your hardware configuration The program 13706CFG EXE can be used to configure 13706BMP For further information on 13706CFG refer to the 13706CFG Users Manual document number X31B B 001 xx S1D1...

Page 308: ...play surfaces see Section Display Surfaces on page 5 move n Automatically moves the sub window for n seconds To move the sub window indefinitely set n 1 noinit Skips full register initialization Only registers used for changing the color depth bpp are updated Additionally some registers are read to determine infor mation such as display size r90 Enables SwivelView 90 mode counter clockwise hardwar...

Page 309: ...splay surfaces that may be selected When ds 0 bmpfile1 bmp is displayed in the main window If ds n is not specified on the command line this setting is automatically used when bmpfile2 bmp is not provided This should be chosen when a sub window is not required When ds 1 bmpfile1 bmp is displayed in the main window and also in the sub window Note that only a portion of bmpfile1 bmp is displayed if ...

Page 310: ...mp bmpfile1 bmp ds 0 r90 To display the same bmp image in both the main window and the sub window type the following 13706bmp bmpfile1 bmp ds 1 To display different bmp images independently in the main and sub windows and have the sub window move indefinitely within the main window type the following 13706 bmpfile1 bmp bmpfile2 bmp ds 2 move 1 Comments 13706BMP displays only Windows BMP format ima...

Page 311: ...ating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are ...

Page 312: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Windows CE 2 x Display Drivers X31B E 001 04 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 313: ...is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 4 8 and 16 bit per pixel SwivelView 90 degree 180 degree and 270 degree modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd e...

Page 314: ...oject by following the procedure documented in Creating a New Project Directory from the Windows CE ETK V2 0 Alternately use the current DEMO7 project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO7 project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu...

Page 315: ...06 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODE0 H for the default settings of the driver If the default does not match the configuration you are building for then MODE0 H will have to be regenerated with the correct informa...

Page 316: ... icon i e X86 DEMO7 13 Type BLDDEMO ENTER at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriate 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install Platf...

Page 317: ... wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13706 1 echo off 6 Make an S1D13706 directory under x wince platform cepc drivers display and copy the S1D13706 driver source code into x wince platform cepc drivers dis play S1D13706 7 Edit the file x wince platform cepc drivers displ...

Page 318: ...number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODE0 H in x wince platform cepc drivers display S1D13706 replacing the original configura tion file 10 Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotat...

Page 319: ...ay Drivers S1D13706 Issue Date 01 05 25 X31B E 001 04 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO ENTER at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN ...

Page 320: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 321: ...pecific features ENABLE_CLOCK_CHIP This option is used to enable support for the ICD2061A clock generator This clock chip is used on the S5U13706B00C evaluation board The S1D13706 display drivers can program the clock chip to support the frequencies required in the MODE tables If you are not using the S5U13706B00C evaluation adapter you should disable this option EpsonMessages This debugging optio...

Page 322: ... of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will de...

Page 323: ...E Platform Builder supported platforms By default the 13706CFG program assumes PCI addressing for the S5U13706B00C evaluation board This means that the display driver will automatically locate the S1D13706 by scanning the PCI bus currently only supported for the CEPC platform If you select the address option Other and fill in your own custom addresses for the registers and video memory then the di...

Page 324: ...Page 14 Epson Research and Development Vancouver Design Center S1D13706 Windows CE 2 x Display Drivers X31B E 001 04 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 325: ...ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epso...

Page 326: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Wind River WindML v2 0 Display Drivers X31B E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 327: ...utility 13706CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to develop their own drivers for WindML v...

Page 328: ... Tornado target config pcPentium config h with the file x 13706 8bpp File config h or x 13706 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar sel...

Page 329: ... comments follow these steps a In the Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch fro...

Page 330: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Wind River WindML v2 0 Display Drivers X31B E 002 03 Issue Date 01 04 06 THIS PAGE LEFT BLANK ...

Page 331: ...luating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows ar...

Page 332: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Wind River UGL v1 2 Display Drivers X31B E 003 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 333: ...t driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx This d...

Page 334: ...in modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13706 8bpp File config h or x 13706 16bpp File config h The new config h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Bui...

Page 335: ...6bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A properties win dow will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 8 Compi...

Page 336: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Wind River UGL v1 2 Display Drivers X31B E 003 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 337: ...ownload and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered...

Page 338: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 THIS PAGE LEFT BLANK ...

Page 339: ...h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx Note The Linux console driver is provided as reference source code only The driver is in tended to provide a basis for OE...

Page 340: ...n www erd epson com was built using Red Hat Linux 6 1 kernel version 2 2 17 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13706 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13706 a...

Page 341: ...ion Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration choose File Export and select the C Header File for S1D13706 Generic Drivers option Save the new configuration as s1d13706 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video options From the command prompt in the directory ...

Page 342: ...he lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13706 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfr...

Page 343: ...erd epson com was built using Red Hat Linux 6 1 kernel version 2 4 5 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13706 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13706 archive ...

Page 344: ...erate the required header file For information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration choose File Export and select the C Header File for S1D13706 Generic Drivers option Save the new configuration as s1d13706 h in the usr src linux drivers video replacing t...

Page 345: ... to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13706 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the neces...

Page 346: ...Page 10 Epson Research and Development Vancouver Design Center S1D13706 Linux Console Driver X31B E 004 02 Issue Date 01 09 19 THIS PAGE LEFT BLANK ...

Page 347: ...t but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Co...

Page 348: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 QNX Photon v2 0 Display Driver X31B E 005 02 Issue Date 01 09 10 THIS PAGE LEFT BLANK ...

Page 349: ... driver is designed around a common configuration include file called S1D13706 h which is generated by the configuration utility 13706CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13706CFG see the 13706CFG Configuration Program User Manual document number X31B B 001 xx Note The QNX display drivers are provided ...

Page 350: ...is unpacks the files into the directory Project gddk_1 0 devg S1D13706 Configure the Driver The files s1d13706_16 h and s1d13706_8 h contain register values required to set the screen resolution color depth bpp display type rotation etc The s1d13706 h file included with the drivers may not contain applicable values and must be regenerated The configuration program 13706CFG can be used to build new...

Page 351: ...graphics dldevg S1D13506 so g640x480x8 I0 d0x0 0x0 640 480 8 Epson io graphics dldevg S1D13506 so g640x480x16 I0 d0x0 0x0 640 480 16 Epson Run the Driver Note For the remaining steps the S5U13706B00C evaluation board must be installed on the test platform It is recommended that the driver be verified before starting QNX with the S1D13706 as the primary display To verify the driver type the followi...

Page 352: ...ch and Development Vancouver Design Center S1D13706 QNX Photon v2 0 Display Driver X31B E 005 02 Issue Date 01 09 10 Comments To restore the display driver to the default comment out changes made to the trap file crt NODE ...

Page 353: ...ating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are ...

Page 354: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Windows CE 3 x Display Drivers X31B E 006 01 Issue Date 01 05 25 THIS PAGE LEFT BLANK ...

Page 355: ...ver is capable of 4 8 and 16 bit per pixel landscape modes no rotation and 8 and 16 bit per pixel SwivelView 90 degree 180 degree and 270 degree modes This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd...

Page 356: ...ng on the Microsoft Windows CE Platform Builder icon 4 Create a new project a Select File New b In the dialog box select the Platforms tab c In the platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC ...

Page 357: ...he Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WI...

Page 358: ...rogram User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 12 From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Param...

Page 359: ...on oak misc call wince x86 i486 CE MAXALL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 4 Generate the build environment by calling cepath bat 5 Create a new folder called S1D13706 under x wince300 platform cepc drivers dis play and copy the S1D13706 driver source code into x wince300 platform cepc driv ers display S1D13706 6 Edit the file x wince300 platform cepc drivers display...

Page 360: ... information on how to use 13706CFG refer to the 13706CFG Configuration Program User Manual document number X31B B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13706 WinCE Drivers Save the new configuration as MODE0 H in the wince300 platform cepc drivers display replacing the original configuration file 9 Edit the file P...

Page 361: ...vers S1D13706 Issue Date 01 05 25 X31B E 006 01 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO ENTER at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin ...

Page 362: ...ice a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to C...

Page 363: ...ures EnablePreferVmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option for systems with limited off screen memory ENABLE_CLOCK_CHIP This option is used to enable support for the ICD2061A clock generator This clock chip is used on the S5U13706...

Page 364: ... for correct display on a mono panel For use with color panels this option should not be enabled Mode File The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13706CFG EXE The display driver comes with example MODE tables By default only MODE0 H is used by the disp...

Page 365: ...ion video performance and power off capabilities The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of Windows CE Disp...

Page 366: ... mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is L...

Page 367: ...ay Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S1D13706 sources and change the line CDEF...

Page 368: ... scanning the PCI bus currently only supported for the CEPC platform If you select the address option Other and fill in your own custom addresses for the registers and video memory then the display driver will not scan the PCI bus and will use the specific addresses you have chosen If you are running 13706CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab...

Page 369: ...ut only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corpo...

Page 370: ...Page 2 Epson Research and Development Vancouver Design Center S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 THIS PAGE LEFT BLANK ...

Page 371: ...y of LCD controllers with Windows NT 4 0 2000 The file S1D13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Installation Windows NT Version 4 0 All evaluation boards require the driver to be installed as follows 1 Install the evaluation board in the computer and boot th...

Page 372: ...nd it 7 Click NEXT 8 Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN 9 Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT 3 Select ADD ...

Page 373: ...ows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Go to the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ...

Page 374: ... Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 Click NEXT Windows will search the floppy drive and fail 4 Windows will attempt to load the new hardware as a Standard VGA Card 5 Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE 6 Select NO for Windows to DETECT NEW HARDWARE 7 Click NEXT 8 Select OTHER DEVICES from HARDWARE TYPE a...

Page 375: ...lick NEXT 5 Select OTHER DEVICES and click NEXT 6 Click Have Disk 7 Specify the location of the driver files and click OK 8 Click Next 9 Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Windows will detect the card 3 Select DRIVER FROM DISK PROVIDED BY MANUFACTURER 4 Click OK 5 Specify a path to the loc...

Page 376: ...he computer and boot the computer 2 Go to the CONTROL PANEL and select ADD NEW HARDWARE 3 Click NEXT 4 Select NO and click NEXT 5 Select OTHER DEVICES from the HARDWARE TYPES list 6 Click HAVE DISK 7 Specify the location of the driver files and click OK 8 Select the file S1D13XXX INF and click OK 9 Click OK 10 The EPSON PCI Bridge Card should be selected in the list window 11 Click NEXT 12 Click N...

Page 377: ...is document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seik...

Page 378: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 379: ...6 1 PCI Bus Support 20 6 2 Direct Host Bus Interface Support 20 6 3 S1D13706 Embedded Memory 20 6 4 Manual Software Adjustable LCD Panel Positive Power Supply VDDH 20 6 5 Manual Software Adjustable LCD Panel Negative Power Supply VLCD 21 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM 22 6 7 Passive Active LCD Panel Support 22 6 7 1 Buffered LCD Connector 22 6 7 2 Extended LCD Co...

Page 380: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 381: ...es Figure 3 1 Configuration DIP Switch SW1 Location 9 Figure 3 2 Configuration Jumper JP1 Location 11 Figure 3 3 Configuration Jumper JP2 Location 12 Figure 3 4 Configuration Jumper JP3 Location 12 Figure 3 5 Configuration Jumper JP4 Location 13 Figure 3 6 Configuration Jumper JP5 Location 13 Figure 3 7 Configuration Jumper JP6 Location 14 Figure 3 8 Configuration Jumper JP7 Location 14 Figure 7 1...

Page 382: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 383: ... The board is designed as an evaluation platform for the S1D13706 Embedded Memory LCD Controller This user manual is updated as appropriate Please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our documentati...

Page 384: ...20V to 40V Manual or software adjustable negative LCD bias power supply from 24V to 8V Software adjustable backlight intensity support 4 8 bit 3 3V or 5V single monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V single color passive LCD panel support 9 12 18 bit 3 3V or 5V active matrix TFT LCD panel support Direct interface for 18 bit Epson D TFD LCD panel support Direct interface for 18 ...

Page 385: ...and seven jumpers which allow both evaluation board and S1D13706 LCD controller to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The S1D13706 has configuration inputs CNF 7 0 which are read on the rising edge of RESET In order to configure the S1D13706 for multiple Host Bus Interfaces a ten position DIP switch S1 is required The following figure shows the locatio...

Page 386: ...to 1 Table 3 1 Configuration DIP Switch Settings Switch S1D13706 Signal Value on this pin at rising edge of RESET is used to configure Closed On 1 Open Off 0 SW1 3 1 CNF 2 0 Select host bus interface as follows CNF2 CNF1 CNF0 Host Bus Interface 0 0 0 SH 4 SH 3 0 0 1 MC68K 1 0 1 0 MC68K 2 0 1 1 Generic 1 1 0 0 Generic 2 1 0 1 RedCap 2 1 1 0 DragonBall 1 1 1 Reserved Note The host bus interface is 1...

Page 387: ...D13706 Hardware Functional Specification document number X28B A 001 xx for details Note When configured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 Figure 3 2 Configuration Jumper JP1 Location Table 3 2 Jumper Summary Jumper Function Position 1 2 Position 2 3 No Jumper JP1 GPIO0 Connection GPIO0 connected to SW1 9 for hardware video inver...

Page 388: ...ock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U5 Figure 3 3 Configuration Jumper JP2 Location JP3 CLKI Source JP2 selects the source for the CLKI Position 1 2 sets the CLKI2 source to VCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U6 Figure 3 4 Configuration Jumper JP3 Lo...

Page 389: ...ult setting Position 2 3 inverts the GPO signal before sending it to H1 Figure 3 5 Configuration Jumper JP4 Location JP5 Contrast adjust for ve LCD bias VDDH JP5 selects the type of control used for contrast adjustment of the ve LCD bias VDDH Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adjustment using potentiometer R24 defau...

Page 390: ...ured for Sharp HR TFT or Epson D TFD panels JP1 must be set to no jumper and JP6 must be set to position 2 3 Figure 3 7 Configuration Jumper JP6 Location JP7 Contrast adjust for ve LCD bias VLCD JP7 selects the type of control used for contrast adjustment of the ve LCD bias VLCD Position 1 2 selects software control of the contrast adjustment Position 2 3 selects manual control of the contrast adj...

Page 391: ... Mapping S1D13706 Pin Name Generic 1 Generic 2 Hitachi SH 3 SH 4 Motorola MC68K 1 Motorola MC68K 2 Motorola REDCAP2 Motorola MC68EZ328 MC68VZ328 DragonBall AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 AB0 A01 A0 A01 LDS A0 A01 A01 DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 2 D 15 0 D 15 0 CS External Decode CSn External Decode CSn CSA M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK...

Page 392: ...o DB6 of the S1D13706 10 Connected to DB7 of the S1D13706 11 Ground 12 Ground 13 Connected to DB8 of the S1D13706 14 Connected to DB9 of the S1D13706 15 Connected to DB10 of the S1D13706 16 Connected to DB11 of the S1D13706 17 Ground 18 Ground 19 Connected to DB12 of the S1D13706 20 Connected to DB13 of the S1D13706 21 Connected to DB14 of the S1D13706 22 Connected to DB15 of the S1D13706 23 Conne...

Page 393: ...d to A7 of the S1D13706 9 Ground 10 Ground 11 Connected to A8 of the S1D13706 12 Connected to A9 of the S1D13706 13 Connected to A10 of the S1D13706 14 Connected to A11 of the S1D13706 15 Connected to A12 of the S1D13706 16 Connected to A13 of the S1D13706 17 Ground 18 Ground 19 Connected to A14 of the S1D13706 20 Connected to A15 of the S1D13706 21 Connected to A16 of the S1D13706 22 Not connecte...

Page 394: ... 9 D0 D4 D0 R2 1 D4 R3 1 D4 R2 1 D8 B5 1 G1 G2 G4 G4 G4 FPDAT5 11 D1 D5 D1 B1 1 D5 G2 1 D5 B1 1 D9 R5 1 G0 G1 G3 G3 G3 FPDAT6 13 D2 D6 D2 G1 1 D6 B1 1 D6 G1 1 D10 G4 1 B2 B3 B5 B5 B5 FPDAT7 15 D3 D7 D3 R1 1 D7 R1 1 D7 R1 1 D11 B3 1 B1 B2 B4 B4 B4 FPDAT8 17 driven 0 driven 0 driven 0 driven 0 driven 0 D4 G3 1 B0 B1 B3 B3 B3 FPDAT9 19 driven 0 driven 0 driven 0 driven 0 driven 0 D5 B2 1 driven 0 R0 ...

Page 395: ...d for the HR TFT or D TFD interfaces and are not available as GPIO pins Table 5 2 Extended LCD Signal Connector H2 Pin Name Connector Pin No Monochrome Passive Panel Color Passive Panel Color TFT Panel Single Single Others HR TFT1 D TFD1 Format 1 Format 2 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit 18 bit GPIO0 1 GPIO0 PS XINH GPIO1 3 GPIO1 CLS YSCL GPIO2 5 GPIO2 REV FR GPIO3 7...

Page 396: ... Memory The S1D13706 has 80K bytes of embedded SRAM The 80K byte display buffer address space is directly and contiguously available through the 17 bit address bus 6 4 Manual Software Adjustable LCD Panel Positive Power Supply VDDH Most passive LCD color and passive single monochrome LCD panels require a positive bias voltage between 24V and 40V The S5U13706B00C uses a Maxim MAX754 LCD Contrast Co...

Page 397: ...LCD can be controlled through software to provide an output voltage from 8V to 24V CVOUT and GPO of the S1D13706 are connected to ADJ and CTRL of MAX749 The output voltage VLCD can be adjusted from 8V to 24V in 64 steps by sending pulses to CVOUT Each CVOUT pulse increments VLCD one step towards 24V When decremented beyond 24V VLCD resets to 8V again In other words 63 pulses equal incrementing 1 s...

Page 398: ...l the necessary signals are provided on the 40 pin LCD connector H1 For connection information refer to Table 5 1 LCD Signal Connector H1 on page 18 6 7 1 Buffered LCD Connector The buffered LCD connector H1 provides the same LCD panel signals as those directly from S1D13706 but with voltage adapting buffers selectable to 3 3V or 5 0V Pin 32 on this connector provides a voltage level of 3 3V or 5 ...

Page 399: ...clock signals to CLKI and CLKI2 Jumpers JP2 and JP3 allow selection of external oscillators U5 and U6 as the clock source for both CLKI and CLKI2 For further information see Table 3 2 Jumper Summary on page 11 7 1 Clock Programming The S1D13706 utilities automatically program the clock generator If manual programming of the clock generator is required refer to the source code for the S1D13706 util...

Page 400: ...rch and Development Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S1D13806 Programming Notes and Examples document number X31B G 003 xx Cypress Semiconductor Corporation ICD2061A Data Sheet 8 2 Document Sources Epson Electronics America Website http www eea epson com Cypress Semiconductor Corporation Website http www cypress com ...

Page 401: ...N5819 Schottky Barrier Rectifier MELF pckg Lite on 1N5819M or equivalent 11 1 H1 HEADER 20X2 20x2 025 sq shrouded header keyed Thomas Betts P N 636 4207 or equivalent 12 1 H2 HEADER 8X2 8x2 025 sq shrouded header keyed Thomas Betts P N 636 1607 or equivalent 13 2 H4 H3 HEADER 17X2 17x2 025 sq unshrouded header 14 2 JP7 JP1 HEADER 2 2x1 1 pitch unshrouded header 15 5 JP2 JP3 JP4 JP5 JP6 HEADER 3 3x...

Page 402: ...ount package Do not purchase supplied by EPSON R D 38 1 U2 LT1117CST 5 5V fixed voltage regulator SOT 223 Linear Technology LT1117CST 5 39 1 U3 74AHC04 SO 14 package NS 74VHC04 or TI 74AHC04 SO 14 package 40 1 U4 ICD2061A Wide SO 16 package Cypress ICD2061A 41 2 U6 U5 Test Socket 14 pin narrow DIP screw machine socket 42 4 U7 U8 U9 U10 74HCT244 SO 20 package 43 1 U11 MAX754 16 pin narrow SO pckg M...

Page 403: ... Fundamental Mode Parallel Resonant Crystal HC49 Low Profile pckg FOXS 143 20 or equivalent 50 7 JP1 JP7 Micro Shunt 51 1 Bracket Computer Bracket Blank PCI Keystone Cat No 9203 52 2 Screw Pan head 4 40 x 1 4 Screw pan head 4 40 x 1 4 please assemble bracket onto board Table 9 1 Parts List Item Qty Designation Part Value Description Manufacturer Part No Assembly Instructions ...

Page 404: ...V R12 330K R10 330K R4 15K R13 330K U1 S1D13706F00A 5 4 3 2 99 98 97 96 95 94 93 92 91 90 89 88 87 35 34 33 32 31 30 29 28 27 24 23 22 21 20 19 18 15 77 6 7 8 9 10 11 12 13 17 85 84 83 82 81 80 79 78 55 56 57 58 59 60 61 64 65 66 67 68 69 70 71 72 73 74 52 53 54 48 46 38 47 45 44 43 42 41 40 39 86 14 25 36 50 62 75 100 16 26 37 49 63 76 1 51 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 A...

Page 405: ... 1 3 GPIO6 1 3 CLKI2 1 CLKI 1 5 6 BUSCLK 1 5 6 5V 5V 12V 5V 5V 3 3V 3 3V 3 3V 3 3V 3 3V 3 3V JP3 HEADER 3 1 2 3 JP2 HEADER 3 1 2 3 C9 0 1u U6 Test Socket 1 8 7 14 NC OUT GND VCC U3F 74AHC04 13 12 14 7 C16 0 1u U5 Test Socket 1 8 7 14 NC OUT GND VCC C17 0 1u U2 LT1117CST 5 3 1 2 VIN ADJ VOUT C13 0 1u C10 0 1u C11 0 1u C12 10u 10V U4 ICD2061A 13 3 5 1 2 12 14 16 4 6 7 11 15 8 9 10 VDD AVDD GND S0 CL...

Page 406: ... FPDAT 17 0 1 VLCD 4 VDDH 4 GPIO3 1 CVOUT 1 4 GPIO4 1 GPIO5 1 2 GPIO2 1 GPIO1 1 GPIO6 1 2 GPIO0 1 GPO 1 4 PWMOUT 1 FPSHIFT 1 DRDY 1 FPFRAME 1 FPLINE 1 LCDVCC LCDVCC LCDVCC 12V LCDVCC LCDVCC 3 3V C19 0 1u H1 HEADER 20X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 U7 74HCT244 2 4 6 8 11 13 15 17 1 19 18 16 14 12 9 7 5 3 20 10 1A1 1A2...

Page 407: ...V 5V LCDVCC U13 MAX749 1 2 3 4 5 6 7 8 V ADJ CTRL FB GND DLOW DHI CS C29 0 1u L2 47uH R26 470 C30 68u 10V Q4 MMBT2222A D2 1N5819 1 2 R28 100K C26 10u 10V C25 0 1u Q2 MMFT3055VL 1 2 3 4 R27 22K R25 0 22 1 4W R30 1 2M Q1 MMBT3906L 3 1 2 C24 10u 63V C22 22u 10V R31 500K POT 1 3 2 R29 100K C27 0 1u R20 80K U12 LT1117CM 3 3 3 1 2 VIN ADJ VOUT JP7 HEADER 2 1 2 D1 1N5819 1 2 R23 301 1 C31 1n C32 10u 63V ...

Page 408: ... 5V 5V 12V 12V 5V 5V C36 33u 20V PCIB1 PCI B 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 52 53 54 55 56 57 58 59 60 61 62 12V TCK GND TDO 5V 5V INTB INTD PRSNT 1 RESERVED PRSNT 2 RESERVED GND CLK GND REQ VI O AD31 AD29 GND AD27 AD25 3 3V C BE3 AD23 GND AD21 AD19 3 3V AD17 C BE2 GND IRDY 3 3V DEVSEL GND LOCK PER...

Page 409: ...5 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 IO1 IO2 IO3 nCE GND Vccint...

Page 410: ... 34 Epson Research and Development Vancouver Design Center S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 11 Board Layout Figure 11 1 S5U13706B00C Board Layout ...

Page 411: ... Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 M...

Page 412: ...Page 36 Epson Research and Development Vancouver Design Center S1D13706 S5U13706B00C Rev 1 0 Evaluation Board User Manual X31B G 004 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 413: ...use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark o...

Page 414: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 415: ...s 8 2 1 1 Overview 8 2 1 2 Card Access Cycles 8 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 Toshiba TMPR3905 12 to S1D13706 Interface 12 4 1 Hardware Description 12 4 2 S1D13706 Hardware Configuration 14 4 3 Memory Mapping and Aliasing 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 7 1 ...

Page 416: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 417: ...X31B G 002 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Configuration Options 14 Table 4 2 CLKI to BCLK Divide Selection 14 List of Figures Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle 9 Figure 2 2 Toshiba 3905 12 PC Card IO Cycle 9 Figure 4 1 S1D13706 to TMPR3905 12 Direct Connection 12 ...

Page 418: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 419: ...1D13706 Embedded Memory LCD Controller and the Toshiba MIPS TMPR3905 3912 processors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We...

Page 420: ...s The 16 bit PC Card slots provide a 26 bit multiplexed address and additional control signals which allow access to three 64M byte address ranges IO memory and attribute space The signal CARDREG selects memory space when high and attribute or IO space when low Memory and attribute space are accessed using the write and read enable signals WE and RD When CARDREG is low card IO space is accessed us...

Page 421: ... illustrates a typical memory attribute cycle on the Toshiba 3905 12 PC Card bus Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle Figure 2 2 Toshiba 3905 12 PC Card IO Cycle illustrates a typical IO cycle on the Toshiba 3905 12 PC Card bus Figure 2 2 Toshiba 3905 12 PC Card IO Cycle A 25 0 CARD1CSL RD CARD1WAIT D 31 16 CARDREG CARD1CSH WE ALE A 25 0 CARD1CSL CARDIORD CARD1WAIT D 31 16 CAR...

Page 422: ...S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Config uration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Names Toshiba ...

Page 423: ...S1D13706 M R memory register selects between memory or register accesses This signal may be connected to an address line allowing system address A17 to be connected to the M R line This address line must be generated from the external latch used to provide the upper addresses to the S1D13706 WE1 is connected to CARD1CSH and is the high byte enable for both read and write cycles WE0 is connected to...

Page 424: ...implementation and should be tied high connected to HIO VDD A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram demonstrates a typical implementation of the TMPR3905 12 to S1D13706 interface Figure 4 1 S1D13706 to TMPR3905 12 Direct Connection WE0 RD DB 7 0 WAIT S1D13706 RESET AB 16 13 D 31 24 CARD1WAIT A 12 0 TMPR3905 12 pull up Oscillat...

Page 425: ...ous with respect to the S1D13706 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and CLKI2 The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired pixel and frame rates power budget part count maximum S1D13706 clock frequencies The S1D13706 also has internal...

Page 426: ...l registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The registers occupy the range 0h through 1FFFFh while the on chip display memory occupies the range 20000h through 3FFFFh Demultiplexed address lines A 25 18 are ignored Therefore the S1D13706 is aliased 256 times at 256K byte intervals over the 64M byte PC Card slot 1 memory space No...

Page 427: ...ode is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 ...

Page 428: ...search and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Toshiba America Electrical Components Website http ...

Page 429: ...d 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 North America Epson Electronics America Inc 150 River Oaks Parkway San J...

Page 430: ...Page 18 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X31B G 002 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 431: ...t but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Co...

Page 432: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 433: ... PC Card Overview 8 2 1 2 Memory Access Cycles 8 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 PC Card to S1D13706 Interface 12 4 1 Hardware Connections 12 4 2 S1D13706 Hardware Configuration 13 4 3 Register Memory Mapping 13 5 Software 14 6 References 15 6 1 Documents 15 6 2 Document Sources 15 7 Technical Support 16 7 1 EPSON LCD Contr...

Page 434: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 435: ...1B G 005 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 2 CLKI to BCLK Divide Selection 13 Table 4 1 Summary of Power On Reset Configuration Options 13 List of Figures Figure 2 1 PC Card Read Cycle 9 Figure 2 2 PC Card Write Cycle 9 Figure 4 1 Typical Implementation of PC Card to S1D13706 Interface 12 ...

Page 436: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the PC Card Bus X31B G 005 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 437: ... Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our do...

Page 438: ...s the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 15 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 ca...

Page 439: ...lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus Figure 2 1 PC Card Read Cycle Figure 2 2 illustrates a typical memory access write cycle on the PC Card bus Figure 2 2 PC Card Write Cycle A 25 0 CE1 OE WAIT ADDRESS VALID DATA VALID Hi Z Hi Z D 15 0 REG CE2 Transfer Start Transfer Complete A 25 0 CE...

Page 440: ...sed the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Note Although a clock is not directly supplied by the PC Card interface one is required by the S1D13706 Generic 2 Host Bus ...

Page 441: ...ress line allowing system address A17 to be connected to the M R line WE1 is the high byte enable for both read and write cycles and connects to the PC Card high byte chip select signal CE2 WE0 connects to WE the write enable signal form the PC Card bus and must be driven low when the PC Card bus is writing data to the S1D13706 RD connects to OE the read enable signal from the PC Card bus and must...

Page 442: ...critical nor does it have to be synchronous to the bus signals it may be the same as CLKI2 BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO VDD The following diagram shows a typical implementation of the PC Card to S1D13706 interface Figure 4 1 Typical Implementation of PC Card to S1D13706 Interface RD WR RD DB 15 0 WAIT CLKI S1D13706...

Page 443: ...pies the second 128K byte block The PC Card socket provides 64M bytes of memory address space However the S1D13706 only needs a 256K byte block of memory to accommodate its 80K byte display buffer and register set For this reason only address bits A 17 0 are used while A 25 17 are ignored The S1D13706 s memory and registers are aliased every 256K bytes for a total of 256 times in the 64M byte PC C...

Page 444: ...e test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are availabl...

Page 445: ...velopment Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources PC Card website http www pc card com Epson Electronics America website h...

Page 446: ...x 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics Ameri...

Page 447: ...only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporat...

Page 448: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Power Consumption X31B G 006 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 449: ...of toggling pins and other factors the higher the BCLK the higher the CPU performance and power consumption VDD voltage level the voltage level affects power consumption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow t...

Page 450: ...it Single Color Format 2 CLKI 6 MHz CLKI2 6 MHz 1 16 1 bpp 6 58 3 02 0 00 1 8 2 bpp 7 76 3 02 0 00 1 4 4 bpp 8 80 3 02 0 00 1 2 8 bpp 10 61 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Color CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 11 16 3 02 0 00 LCD Panel 60Hz 320x240 4 bit Single Monochrome CLKI 6 MHz CLKI2 6 MHz 1 2 8 bpp 9 43 3 02 0 00 LCD Panel 60Hz 320x240 18 bit TFT CLKI 6 MHz CLKI2 6 MHz 1 2 8 b...

Page 451: ...otal Power Consumption in mW show that S1D13706 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU performance and LCD frame rate whereas power save mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13706 can be configured to be an extremely power efficient LCD Controller with hi...

Page 452: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Power Consumption X31B G 006 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 453: ...e this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of ...

Page 454: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 455: ...s 8 2 1 1 Overview 8 2 1 2 LCD Memory Access Cycles 9 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 VR4102 VR4111 to S1D13706 Interface 12 4 1 Hardware Description 12 4 2 S1D13706 Hardware Configuration 13 4 3 NEC VR4102 VR4111 Configuration 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 ...

Page 456: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 457: ...Date 01 02 23 X31B G 007 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 2 CLKI to BCLK Divide Selection 13 Table 4 1 Summary of Power On Reset Configuration Options 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles 9 Figure 4 1 Typical Implementation of VR4102 VR4111 to S1D13706 Interface 12 ...

Page 458: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 459: ...icroprocessor The NEC VR4102 and VR4111 microprocessors are specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document ...

Page 460: ...or is designed around the RISC architecture developed by MIPS The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and the VR4111 is designed around the 80 100MHz VR4110 core These microprocessors support 64 bit processing The CPU communicates with the Bus Control Unit BCU through its internal SysAD bus The BCU in turn communicates with external devices with its ADD and DATA buss...

Page 461: ...riven low The read enable RD or write enable WR signals are driven low for the appropriate cycle LCDRDY is driven low by the S1D13706 to insert wait states into the cycle The system high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Figure 2 1 NEC VR4102 VR4111 Read Write Cycles shows the read and write cycles to the LCD Controller Interface Figure 2 1 NEC VR4102 VR41...

Page 462: ...nd individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of ...

Page 463: ... line WE1 connects to SHB the high byte enable signal from the NEC VR4102 4111 which in conjunction with address bit 0 allows byte steering of read and write opera tions WE0 connects to WR the write enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is writing data to the S1D13706 RD connects to RD the read enable signal from the NEC VR4102 4111 and must be driven l...

Page 464: ...attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO VDD The following diagram shows a typical implementation of the VR4102 VR4111 to S1D13706 interface Figure 4 1 Typical Implementation of VR4102 VR4111 to S1D13706 Interface WE1 WE0 DB 15 0 WAIT RD CLKI S1D13706 CS RESET...

Page 465: ...uired for this implementation of a S1D13706 to NEC VR4102 4111 interface Table 4 2 CLKI to BCLK Divide Selection Table 4 1 Summary of Power On Reset Configuration Options S1D13706 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 0 CNF 2 0 100 Generic 2 Host Bus Interface CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus inte...

Page 466: ...cupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block The starting address of the S1D13706 internal registers is located at 0A00_0000h and the starting address of the display buffer is located at 0A02_0000h These blocks are aliased over the entire 16M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded The NEC...

Page 467: ...for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers a...

Page 468: ... s Manual Epson Research and Development Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources NEC Electronics Inc website http www nece...

Page 469: ...ng Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America...

Page 470: ...Page 18 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4102 VR4111 Microprocessors X31B G 007 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 471: ...his document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Sei...

Page 472: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 473: ... 8 2 1 1 Overview 8 2 1 2 LCD Memory Access Signals 9 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 VR4181A to S1D13706 Interface 12 4 1 Hardware Description 12 4 2 S1D13706 Hardware Configuration 13 4 3 NEC VR4181A Configuration 14 5 Software 15 6 References 16 6 1 Documents 16 6 2 Document Sources 16 7 Technical Support 17 7 1 Epson LC...

Page 474: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 475: ...rocessor S1D13706 Issue Date 01 02 23 X31B G 008 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Configuration Options 13 Table 4 2 CLKI to BCLK Divide Selection 13 List of Figures Figure 4 1 Typical Implementation of VR4181A to S1D13706 Interface 12 ...

Page 476: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 477: ...microprocessor The NEC VR4181A microprocessor is specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before begi...

Page 478: ...s an overview of the operation of the CPU bus to establish interface requirements 2 1 1 Overview The NEC VR4181A is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 100MHz VR4110 CPU core which supports the MIPS III and MIPS16 instruction sets The CPU communicates with external devices via an ISA interface While the VR4181A has an embedded LCD cont...

Page 479: ...signals obey ISA signalling rules A 16 0 is the address bus UBE is the high byte enable active low LCDCS is the chip select for the S1D13706 active low D 15 0 is the data bus MEMRD is the read command active low MEMWR is the write command active low MEMCS16 is the acknowledge for 16 bit peripheral capability active low IORDY is the ready signal from S1D13706 SYSCLK is the prescalable bus clock opt...

Page 480: ...nd individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of ...

Page 481: ...nects to UBE the high byte enable signal from the NEC VR4181A which in conjunction with address bit 0 allows byte steering of read and write operations WE0 connects to MEMWR the write enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is writing data to the S1D13706 RD connects to MEMRD the read enable signal from the NEC VR4181A and must be driven low when the NEC VR41...

Page 482: ... a cycle MEMCS16 of the NEC VR4181A is connected to LCDCS to signal that the S1D13706 is capable of 16 bit transfers BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO VDD The diagram below shows a typical implementation of the VR4181A to S1D13706 interface Figure 4 1 Typical Implementation of VR4181A to S1D13706 Interface WE1 WE0 DB 15...

Page 483: ...the configuration required for this implementation of a S1D13706 to NEC VR181A interface Table 4 1 Summary of Power On Reset Configuration Options S1D1370 6 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 0 CNF 2 0 100 Generic 2 Host Bus Interface CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface Little Endian bus...

Page 484: ...K bytes With this configuration the S1D13706 internal registers starting address is located at physical memory location 133C_0000h and the display buffer is located at memory location 133E_0000h The NEC VR4181A must be configured through its internal registers to map the S1D13706 to the external LCD controller space The following register values must be set Register LCDGPMD at address 0B00_032Eh m...

Page 485: ... the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are avail...

Page 486: ... Epson Research and Development Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources NEC Electronics Inc website http www necel com Eps...

Page 487: ...ong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Eps...

Page 488: ...Page 18 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the NEC VR4181A Microprocessor X31B G 008 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 489: ... this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of S...

Page 490: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 491: ...se Chip Select Module GPCM 11 2 3 2 User Programmable Machine UPM 12 3 S1D13706 Host Bus Interface 13 3 1 Host Bus Interface Pin Mapping 13 3 2 Host Bus Interface Signals 14 4 MPC821 to S1D13706 Interface 15 4 1 Hardware Description 15 4 2 MPC821ADS Evaluation Board Hardware Connections 16 4 3 S1D13706 Hardware Configuration 18 4 4 Register Memory Mapping 18 4 5 MPC821 Chip Select Configuration 19...

Page 492: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 493: ...erface Pin Mapping 13 Table 4 1 List of Connections from MPC821ADS to S1D13706 16 Table 4 3 CLKI to BCLK Divide Selection 18 Table 4 2 Summary of Power On Reset Configuration Options 18 List of Figures Figure 2 1 Power PC Memory Read Cycle 9 Figure 2 2 Power PC Memory Write Cycle 10 Figure 2 3 GPCM Memory Devices Timing 12 Figure 4 1 Typical Implementation of MPC821 to S1D13706 Interface 15 ...

Page 494: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 495: ...dded Memory LCD Controller and the Motorola MPC821 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your co...

Page 496: ...ming generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in ...

Page 497: ...ad cycles and low for write cycles AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum leng...

Page 498: ...A31 are ignored For 16 bit transfers data lines D0 through D15 are used and address line A31 is ignored For 8 bit transfers data lines D0 through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry o...

Page 499: ...mpatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing...

Page 500: ...a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral ...

Page 501: ...SET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 3 S1D13706 Hardware Configuration on page 18 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Note The Motorola MPC821 chip select module only handles 16 bit read cycles As the S1D13706 uses the chip selec...

Page 502: ...he M R line WE0 connects to WE1 the low byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the low byte to the S1D13706 WE1 connects to WE0 the high byte enable signal from the MPC821 and must be driven low when the MPC821 is writing the high byte to the S1D13706 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are dri...

Page 503: ...on and should be tied high connected to HIO VDD The following diagram shows a typical implementation of the MPC821 to S1D13706 interface Figure 4 1 Typical Implementation of MPC821 to S1D13706 Interface Table 4 1 List of Connections from MPC821ADS to S1D13706 on page 16 shows the connections between the pins and signals of the MPC821 and the S1D13706 MPC821 S1D13706 A 15 31 D 0 15 CS4 TA WE0 WE1 O...

Page 504: ...are Connections The following table details the connections between the pins and signals of the MPC821 and the S1D13706 Table 4 1 List of Connections from MPC821ADS to S1D13706 MPC821 Signal Name MPC821ADS Connector and Pin Name S1D13706 Signal Name Vcc P6 A1 P6 B1 COREVDD HIOVDD NIOVDD A15 P6 D20 A16 A16 P6 B24 A15 A17 P6 C24 A14 A18 P6 D23 A13 A19 P6 D22 A12 A20 P6 D19 A11 A21 P6 A19 A10 A22 P6 ...

Page 505: ... bit is A0 the next is A1 A2 etc D11 P12 A14 D4 D12 P12 B14 D3 D13 P12 D14 D2 D14 P12 B13 D1 D15 P12 C13 D0 SRESET P9 D15 RESET SYSCLK P9 C2 CLKI CS4 P6 D13 CS TA P6 B6 to inverter enabled by CS WAIT WE0 P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD WR RD GND P12 A1 P12 B1 P12 A2 P12 B2 P12 A3 P12 B3 P12 A4 P12 B4 P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Vss Table 4 1 List of Connections from MPC821ADS to S1D1...

Page 506: ... 3F FFFFh so the S1D13706 is addressed starting at 40 0000h The S1D13706 uses two 128K byte blocks which are selected using A14 from the MPC821 A14 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Table 4 2 Summary of Power On Reset Configuration Options S1D13706 Pin Name value on this ...

Page 507: ...e write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13706 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS asserti...

Page 508: ...be set up so that the S1D13706 memory block is tagged as non cacheable to ensure that accesses to the S1D13706 occurs in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13706 or its display buffer The source code for this test routine is as follows BR4 equ 120 CS4 base register OR4 equ 124 CS4 option register MemStart equ 42 0000 ad...

Page 509: ...or both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers ar...

Page 510: ...PS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Motorola In...

Page 511: ...7 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716...

Page 512: ...Page 24 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MPC821 Microprocessor X31B G 009 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 513: ...d use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark...

Page 514: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 515: ...Transactions 8 2 1 3 Burst Cycles 9 2 2 Chip Select Module 10 3 S1D13706 Host Bus Interface 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signals 12 4 MCF5307 To S1D13706 Interface 13 4 1 Hardware Description 13 4 2 S1D13706 Hardware Configuration 14 4 3 Register Memory Mapping 15 4 4 MCF5307 Chip Select Configuration 15 5 Software 16 6 References 17 6 1 Documents 17 6 2 Document...

Page 516: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 517: ... of Tables Table 3 1 Host Bus Interface Pin Mapping 11 Table 4 2 CLKI to BCLK Divide Selection 14 Table 4 1 Summary of Power On Reset Configuration Options 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle 9 Figure 2 2 MCF5307 Memory Write Cycle 9 Figure 2 3 Chip Select Module Outputs Timing 10 Figure 4 1 Typical Implementation of MCF5307 to S1D13706 Interface 13 ...

Page 518: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X31B G 010 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 519: ...06 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your...

Page 520: ...arate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A31 through A0...

Page 521: ... MCF5307 system bus Figure 2 2 MCF5307 Memory Write Cycle 2 1 3 Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes The TIP Transfer In Progress output is asserted continuously through the burst Burst memory cycles are mainly intended to fill A 31 0 D 31 0 SIZ 1 0 TT 1 0 TS TA BCLK0 Wait States Transfer S...

Page 522: ...which is compatible with most 68K peripherals Chip selects 0 and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each h...

Page 523: ...al Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of eac...

Page 524: ...d to the M R line WE0 connects to BWE0 the low byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the low byte to the S1D13706 WE1 connects to BWE1 the high byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the high byte to the S1D13706 RD and RD WR are read enables for the low order and high order bytes respectively Both sig...

Page 525: ...see Table 4 1 Summary of Power On Reset Configuration Options on page 14 The following diagram shows a typical implementation of the MCF5307 to S1D13706 interface Figure 4 1 Typical Implementation of MCF5307 to S1D13706 Interface MCF5307 S1D13706 A 16 0 D 23 16 CS4 TA BWE1 BWE0 OE BCLK0 AB 16 0 DB 7 0 CS WAIT WE1 WE0 RD WR RD CLKI RESET BS System RESET Note When connecting the S1D13706 RESET pin t...

Page 526: ... this implementation of a S1D13706 to Motorola MFC5307 microprocessor Table 4 2 CLKI to BCLK Divide Selection Table 4 1 Summary of Power On Reset Configuration Options S1D1370 6 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 0 CNF 2 0 011 Generic 1 Host Bus Interface CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interf...

Page 527: ...s required to address the entire address space of the S1D13706 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the S1D13706 The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 WP 0 disable write protect AM 0 enable alternate...

Page 528: ...ble for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drive...

Page 529: ...m SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples document number X31B G 003 xx 6 2 Document Sources Motorola Inc ...

Page 530: ...2 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 ...

Page 531: ...ument but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epso...

Page 532: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Sharp HR TFT Panels X31B G 011 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 533: ... 1 4 AC Gate Driver Power Supplies 10 2 2 HR TFT MOD Signal 11 2 3 S1D13706 to LQ039Q2DS01 Pin Mapping 12 3 Connecting to the Sharp LQ031B1DDxx HR TFT 14 3 1 External Power Supplies 14 3 1 1 Gray Scale Voltages for Gamma Correction 14 3 1 2 Digital Analog Power Supplies 15 3 1 3 DC Gate Driver Power Supplies 15 3 1 4 AC Gate Driver Power Supplies 15 3 2 HR TFT MOD Signal 15 3 3 S1D13706 to LQ031B1...

Page 534: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Sharp HR TFT Panels X31B G 011 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 535: ...ng 11 Table 2 2 S1D13706 to LQ039Q2DS01 Pin Mapping 12 Table 3 1 S1D13706 to LQ031B1DDxx Pin Mapping 16 List of Figures Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage V0 V9 Generation 8 Figure 2 2 Panel Gate Driver DC Power Supplies 9 Figure 2 3 Panel Gate Driver AC Power Supplies 10 Figure 2 4 HR TFT Power On Off Sequence Timing 11 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage V0 V9 Generation...

Page 536: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Sharp HR TFT Panels X31B G 011 04 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 537: ...hese panels are Sharp LQ031B1DDXX 160 x 160 HR TFT panel Sharp LQ039Q2DS01 320 x 240 HR TFT panel The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any develo...

Page 538: ...ON_POWER is supplied by a National Semiconductor micropower Voltage Regulator LP2951 Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage V0 V9 Generation shows the schematic for gray scale voltage generation Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage V0 V9 Generation A4B A7B A6A V9 V3 A1B A3B A8B A1B V4 V2 A2B A7A V 9 1 A9A A6A A6B A5A A9B A8B A4B V8 V7 V1 A8A A3B A2A A9A A6B A5B A4A A4A A2A A1A ...

Page 539: ...chnology high efficiency switching regulator LT1172 The two power supplies can be adjusted through their allowable ranges using the potentiometer VR1 The gate driver logic high power supply VCC is defined as VSS VSHD The typical VCC voltage of 11 7V can be supplied from VSS using a 3 3V zener diode which provides the necessary voltage change Figure 2 2 Panel Gate Driver DC Power Supplies shows the...

Page 540: ...t be alternated every horizontal period and every vertical period The S1D13706 output signal REV accomplishes this function and generates the alternating VCOM signal which is superimposed onto VEE Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 shows the schematic for generating VCOM and VEE Figure 2 3 Panel Gate Driver AC Power Supplies REV VSS VCOM VEE 5V 5V R2 15K 5 R3 22 5 R4 27K 5 C...

Page 541: ... Parameter Min Max Units t1 LCD Power VSHD active to Power Save Mode disabled 0 ns t2 LCD signals low to LCD Power VSHD inactive 0 ns t3 Power Save Mode disabled to LCD Power other active 0 ns t4 LCD Power other inactive to Power Save Mode enabled 0 ns t5 LCD Power other active to MOD active 2 FRAME t6 MOD inactive to LCD Power other inactive 0 ns t7 Power Save Mode disabled to LCD signals active ...

Page 542: ...f gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low See Section 2 1 External Power Supplies on page 8 9 VEE Power supply of gate driver low level See Section 2 1 External Power Supplies on page 8 10 VEE Power supply of gate driver low level See Section 2 1 External Power Supplies on page 8 11 VCOM Common electrode driving signal See Section 2 1 Externa...

Page 543: ...s on page 8 40 V0 Standard gray scale voltage black See Section 2 1 External Power Supplies on page 8 41 V1 Standard gray scale voltage See Section 2 1 External Power Supplies on page 8 42 V2 Standard gray scale voltage See Section 2 1 External Power Supplies on page 8 43 V3 Standard gray scale voltage See Section 2 1 External Power Supplies on page 8 44 V4 Standard gray scale voltage See Section ...

Page 544: ... for Gamma Correction The standard gray scale voltages can be generated using a precise resistor divider network as described in Section 2 1 1 Gray Scale Voltages for Gamma Correction on page 8 Alternately they can be generated using a Sharp gray scale IC The Sharp IR3E203 elimi nates the large resistor network used to provide the 10 gray scale voltages and combines their function into a single IC...

Page 545: ...page 9 and Figure 2 2 Panel Gate Driver DC Power Supplies on page 9 for details on generating VSS VDD and VCC 3 1 4 AC Gate Driver Power Supplies See Section 2 1 4 AC Gate Driver Power Supplies on page 10 and Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 for details on generating VEE and VCOM If the Sharp IR3E203 is used to generate the gray scale voltages the COM signal can be connect...

Page 546: ... gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low See Section 3 1 External Power Supplies on page 14 9 VEE Power supply of gate driver low level See Section 3 1 External Power Supplies on page 14 10 VEE Power supply of gate driver low level See Section 3 1 External Power Supplies on page 14 11 VCOM Common electrode driving signal See Section 3 1 Exter...

Page 547: ...page 14 40 V0 Standard gray scale voltage black See Section 3 1 External Power Supplies on page 14 41 V1 Standard gray scale voltage See Section 3 1 External Power Supplies on page 14 42 V2 Standard gray scale voltage See Section 3 1 External Power Supplies on page 14 43 V3 Standard gray scale voltage See Section 3 1 External Power Supplies on page 14 44 V4 Standard gray scale voltage See Section ...

Page 548: ...ource code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from yo...

Page 549: ...cification Sharp Electronics Corporation LQ031B1DDxx Specification Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 5 2 Document Sources Sharp Electronics Corporation Website http www sharpsma com Epson Electronics America Website http ...

Page 550: ...Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 North America Epson Electronics America Inc 150 River ...

Page 551: ... this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of S...

Page 552: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 553: ...izing 8 2 3 Asynchronous Synchronous Bus Operation 8 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 MC68030 to S1D13706 Interface 12 4 1 Hardware Description 12 4 2 S1D13706 Hardware Configuration 13 4 3 Register Memory Mapping 13 5 Software 14 6 References 15 6 1 Documents 15 6 2 Document Sources 15 7 Technical Support 16 7 1 EPSON LCD C...

Page 554: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 555: ...e 01 02 23 X31B G 013 02 List of Tables Table 2 1 SIZ Signal Encoding 8 Table 2 2 DSACK Decoding 8 Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 Summary of Power On Reset Configuration Options 13 Table 4 2 CLKI to BCLK Divide Selection 13 List of Figures Figure 4 1 Typical Implementation of MC68030 to S1D13706 Interface 12 ...

Page 556: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68030 Microprocessor X31B G 013 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 557: ...dded Memory LCD Controller and the Motorola MC68030 microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your c...

Page 558: ...ng to be transfered for the current bus cycle DSACK1 and DSACK0 the data transfer size acknowledge signals indicate the size of the external port and acknowledge the end of the cycle A0 and A1 determine which portion of the data bus the data is transferred on and whether the address is misaligned 2 3 Asynchronous Synchronous Bus Operation The MC68030 bus can operate asynchronously or synchronously...

Page 559: ...DS the data strobe is used as a condition for valid data on the data bus SIZ selects the active portions of the data bus R W indicates a read or write operation Synchronous bus cycles operate much like asynchronous cycles except only 32 bit port sizes are allowed In this mode the DSACK signals are not required Wait states are inserted with the synchronous signal STERM which signals that the data i...

Page 560: ... by the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Name...

Page 561: ...nal indicates how many bytes are to be transferred during the current cycle WE1 connects to DS the data strobe signal from the MC68030 and must be driven low when valid data has been placed on the bus RD connects to external decode circuitry of SIZ1 one of the transfer size signals of the MC68030 Along with SIZ0 this signal indicates how many bytes are to be transferred during the current cycle RD...

Page 562: ...itry for SIZ1 RD must be connected to the following logic circuitry instead of directly to SIZ1 RD SIZ0 SIZ1 The polarity of the WAIT signal must be selected as active high by connecting CNF5 to NIO VDD see Table 4 1 Summary of Power On Reset Configuration Options on page 13 The diagram below shows a typical implementation of the MC68030 to S1D13706 interface Figure 4 1 Typical Implementation of M...

Page 563: ... 128K byte blocks which are selected using M R from the address decoder The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Registers were located at memory location 10A0 0000h and the display buffer at memory location 10E0 0000h The address space for the S1D13706 is user dependent Table 4 1 Summary of Power On Reset Configur...

Page 564: ...or both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers ar...

Page 565: ...om SPS ADC pps _subpgs _documentation Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Motorola Inc Literatur...

Page 566: ...87 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 271...

Page 567: ...ment but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson...

Page 568: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 569: ...4 Swing Power Supply for the Vertical Drive V0Y and Logic VCCY V5Y Voltages 12 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals 13 3 S1D13706 to D TFD Panel Pin Mapping 14 3 1 LCD Pin Mapping for Horizontal Connector LF37SQT and LF26SCT 15 3 2 LCD Pin Mapping for Y Connector LF37SQT 16 3 3 LCD Pin Mapping for Y Connector LF26SCT 17 4 Power On Off Sequence 18 5 GCP Data Signal 1...

Page 570: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 571: ...T 16 Table 3 3 LCD Pin Mapping for Y Connector Pins for Y Driver LF26SCT 17 Table 4 1 D TFD Power On Off Sequence Timing 18 Table 5 1 GCP Data Bit Chain Values for LF37SQT and LF26SCT 20 List of Figures Figure 2 1 VDDH and VDD Voltage Generation 8 Figure 2 2 VEE Switching Power Supply 9 Figure 2 3 Temperature Compensated VEEY 10 Figure 2 4 VCC Power Supply 11 Figure 2 5 Swing Power Supply for Vert...

Page 572: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 573: ...Film Diode panels the 320 x 240 LF37SQT and the 160 x 240 LF26SCT The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com for the latest revision of this document before beginning any development We appreciate your comment...

Page 574: ...the control signals are inactive Figure 2 1 VDDH and VDD Voltage Generation shows an example implementation which generates VDDH and VDD from 3 3V Figure 2 1 VDDH and VDD Voltage Generation The circuit in Figure 2 1 VDDH and VDD Voltage Generation uses the Vertical Shift Clock control signal YSCL to control a pair of ultrahigh speed P and N channel MOSFET transistors These transistors are used to ...

Page 575: ...ed by the feedback of VEE through D1 This diode feedback causes an overshoot on the rising edge of GPIO5 DD_P1 that is proportional to the output level of VEE This overshoot settles to a steady level after a variable time depending on how high the overshoot was This variable time causes the high speed CMOS inverter U1 to trigger at different times thereby varying the duty cycle of the control inpu...

Page 576: ...el of VEEY The three serially connected diodes are connected to VDDH and grounded through resistor R10 which causes them to be forward biased At room temperature the forward voltage of each diode is approxi mately 0 7V which sets the base voltage of Q1A at 2 4V When the temperature changes the base voltage changes according to the characteristics of the diodes The base voltage at Q1A also appears ...

Page 577: ...izontal logic circuitry must be set at 3 3V The panel must be ready for use before this supply is turned on A general purpose output pin may be used to control VCC GPO on the S1D13706 Figure 2 4 VCC Power Supply shows an example of this power supply The control signal GPO in this implementation activates VCC when it is low Figure 2 4 VCC Power Supply VCC 3 3V 3 3V GPO Q1 NDS9400A SO 2 3 4 5 7 6 8 ...

Page 578: ...so turns on and VCCY vertical logic high potential VCC 3 3V V0Y vertical liquid crystal drive supply swings to VEEY 4 5 when GPIO3 goes low since the reference changes to VEEY from GND for this signal When GPIO3 is high transistor Q1A turns on and Q1b turns off V5Y goes to the level of VEEY VCCY is now referenced to VEEY and its level goes to VEEY VCC Diode D8 forward biases and sets V0Y VDDH 4 5V...

Page 579: ...trol signals must take place at the same time that the swing power supply switches states Figure 2 6 Logic for Vertical Control Signals shows the circuitry required for the vertical control signals The control signals on the left are outputs from the S1D13706 and the derived control signals on the right are connected to the LCD panel Figure 2 6 Logic for Vertical Control Signals V5Y VCCY VCCY VCCY...

Page 580: ...sent to the D TFD panels through two flat cable connectors A 30 pin connector is used for the horizontal drivers and a 12 pin connector for the vertical drivers Both D TFD panels use the same horizontal 30 pin connector but their vertical driver connectors are different The 320x240 LF37SQT connector pins are swapped compared to the 160x240 LF26SCT panel connector The following tables provide pin m...

Page 581: ...7 Blue digital data signal LSB X 10 GCP DRDY PWM output pulse width setting signal X 11 FR GPIO2 AC signal for output X 12 LP FPLINE Data load and start pulse X 13 RES GPIO4 Reset signal for GCP signal X 14 D05 FPDAT0 Red digital data signal MSB X 15 D04 FPDAT1 Red digital data signal X 16 D03 FPDAT2 Red digital data signal X 17 D02 FPDAT9 Red digital data signal X 18 D01 FPDAT10 Red digital data ...

Page 582: ... for output See Section 2 5 Level Shift and Clamp Circuit for Vertical Logic Control Signals on page 13 Y 6 VCCY Power supply for logic high See Section 2 4 Swing Power Supply for the Vertical Drive V0Y and Logic VCCY V5Y Voltages on page 12 Y 7 V5Y Power supply for logic low and liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive V0Y and Logic VCCY V5Y Voltages on page ...

Page 583: ...er supply for liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive V0Y and Logic VCCY V5Y Voltages on page 12 Y 5 NC No Connect No Connect Y 6 V5Y Power supply for logic low and liquid crystal drive See Section 2 4 Swing Power Supply for the Vertical Drive V0Y and Logic VCCY V5Y Voltages on page 12 Y 7 VCCY Power supply for logic high See Section 2 4 Swing Power Supply fo...

Page 584: ...CD signals active Note 1 t2 Power Save Mode Enable bit low to LCD signals active 0 20 ns t3 Power Save Mode Enable bit high to LCD signals low 20 ns t4 LCD signals low to LCD power inactive Note 1 t5 LCD signals active to GPIO5 active 2 FRAME t6 GPIO5 Pin IO Status high to GPIO5 active 20 ns t7 GPIO5 Pin IO Status low to GPIO5 inactive 20 ns t8 GPIO5 inactive to LCD signals low 3 FRAME It is recom...

Page 585: ... pulse For D TFD AC Timing required by the S1D13706 see the S1D13706 Hardware Functional Specification document number X31B A 001 xx 5 1 GCP Data Structure The S1D13706 uses two registers to program the GCP Data D TFD GCP Index Register REG 28h D TFD GCP Data Register REG 2Ch The 256 bit GCP data is organized into 32 8 bit data registers each addressable by the D TFD GCP Index register REG 28h Fig...

Page 586: ...dex Register REG 28h 4 Return to step 2 and repeat until all 32 8 bit segments are programmed The following values must be programmed into the GCP data bit chain for the LF37SQT and LF26SCT D TFD panels Table 5 1 GCP Data Bit Chain Values for LF37SQT and LF26SCT Index Value Index Value Index Value Index Value 00h 52h 08h 49h 10h 2Ah 18h 00h 01h 2Ah 09h 24h 11h 52h 19h 00h 02h 92h 0Ah 92h 12h 49h 1...

Page 587: ...code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from your sal...

Page 588: ...Date 01 02 23 7 References 7 1 Documents Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 7 2 Document Sources Epson Electronics America Website http www eea epson com ...

Page 589: ...F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose C...

Page 590: ...Page 24 Epson Research and Development Vancouver Design Center S1D13706 Connecting to the Epson D TFD Panels X31B G 012 03 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 591: ...n use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft an...

Page 592: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 593: ...nsactions 8 3 S1D13706 Host Bus Interface 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals 11 4 REDCAP2 to S1D13706 Interface 12 4 1 Hardware Description 12 4 2 Hardware Connections 13 4 3 S1D13706 Hardware Configuration 15 4 4 Register Memory Mapping 15 4 5 REDCAP2 Chip Select Configuration 16 5 Software 17 6 References 18 6 1 Documents 18 6 2 Document Sources 18 7 Technica...

Page 594: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 595: ... X31B G 014 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 10 Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C 13 Table 4 2 Summary of Power On Reset Options 15 List of Figures Figure 2 1 REDCAP2 Memory Read Cycle 9 Figure 2 2 REDCAP2 Memory Write Cycle 9 Figure 4 1 Typical Implementation of REDCAP2 to S1D13706 Interface 12 ...

Page 596: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 597: ...n the S1D13706 Embedded Memory LCD Controller and the Motorola REDCAP2 processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America Website at www eea epson com for the latest revision of this document before beginning any development We apprecia...

Page 598: ...the MCU clock and is selected disabled in the Clock Control Register CKCTL REDCAP2 can generate up to 6 independent chip select outputs Each chip select has a memory range of 16M bytes and can be independently programmed for wait states and port size Note REDCAP2 does not provide a wait or termination acknowledge signal to external devic es Therefore all external devices must guarantee a fixed cyc...

Page 599: ...4 02 Figure 2 1 REDCAP2 Memory Read Cycle on page 9 illustrates a typical memory read cycle on the REDCAP2 bus Figure 2 1 REDCAP2 Memory Read Cycle Figure 2 2 REDCAP2 Memory Write Cycle on page 9 illustrates a typical memory write cycle on the REDCAP2 bus Figure 2 2 REDCAP2 Memory Write Cycle A 21 0 CS CLK D 15 0 R W OE EB0 1 A 21 0 CS CLK D 15 0 R W OE EB0 1 ...

Page 600: ...by the S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configu ration For details on S1D13706 configuration see Section 4 3 S1D13706 Hardware Configuration on page 15 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Names REDCA...

Page 601: ... host bus interface with big endian mode M R memory register selects between memory or register access It may be connected to an address line allowing REDCAP2 bus address A17 to be connected to the M R line CS Chip Select must be driven low whenever the S1D13706 is accessed by the REDCAP2 bus RD WR connects to R W which indicates whether a read or a write access is being performed on the S1D13706 ...

Page 602: ...s between the pins and signals of the REDCAP2 and the S1D13706 see Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C on page 13 The following figure demonstrates a typical implementation of the S1D13706 to REDCAP2 interface Figure 4 1 Typical Implementation of REDCAP2 to S1D13706 Interface REDCAP2 S1D13706 A 16 0 D 15 0 CS1 R W OE EB1 CLK RESET AB 16 0 DB 15 0 CS RD WR RD WE0 CLKI RES...

Page 603: ... REDCAP2 Signal Name REDCAP2ADS Connector and Pin Name S1D13706 Signal Name A17 P9 34 M R A16 P9 33 AB20 A15 P9 32 AB19 A14 P9 31 AB18 A13 P9 30 AB17 A12 P9 29 AB16 A11 P9 28 AB15 A10 P9 27 AB14 A9 P9 26 AB13 A8 P9 25 AB12 A7 P9 24 AB11 A6 P9 23 AB10 A5 P9 22 AB9 A4 P9 21 AB8 A3 P9 20 AB7 A2 P9 19 AB6 A1 P9 18 AB5 A0 P9 17 AB4 D15 P9 16 DB15 D14 P9 15 DB14 D13 P9 14 DB13 D12 P9 13 DB12 D11 P9 12 D...

Page 604: ...pin 13 of U28 on the ADM must be connected to VDD This ensures that the DIR signal of transceivers U17 and U18 is low only during read access even when EBC in the CS1 Control Register is set to 0 CLK0 P24 3 BUSCLK CS1 P9 40 CS R W P9 47 RD WR OE P9 48 RD EB1 P9 46 WE0 EB0 P9 45 WE1 Gnd P24 20 P9 50 Vss Table 4 1 List of Connections from REDCAP2 ADM to S5U13706B00C Continued REDCAP2 Signal Name RED...

Page 605: ...e block In this example the S1D13706 internal registers are accessed starting at address 4100 0000h and the display buffer is accessed starting at address 4102 0000h Each Chip Select on the REDCAP2 is allocated a 16M byte block However the S1D13706 only needs a 256K byte block of memory to accommodate its register set and 80K byte display buffer For this reason only address bits A 17 0 are used wh...

Page 606: ...nction enabled WP 0 writes allowed SP 0 user mode access allowed DSZ 10 16 bit Port EBC 0 assert EB0 1 for both reads and writes WEN 1 EB0 1 negated half a clock earlier during write cycle OEA 1 OE asserted half a clock later during a read cycle CSA 0 Chip Select asserted as early as possible No idle cycle inserted between back to back external transfers EDC 1 an idle cycle is inserted after a rea...

Page 607: ...lable for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display dri...

Page 608: ...fications Rev 1 2ext Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Motorola Literature Distributi...

Page 609: ...042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 33...

Page 610: ...Page 20 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola RedCap2 DSP With Integrated MCU X31B G 014 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 611: ...nt but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson C...

Page 612: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 613: ...The Generic 8 bit Processor System Bus 8 3 S1D13706 Host Bus Interface 9 3 1 Host Bus Interface Pin Mapping 9 3 2 Host Bus Interface Signals 10 4 8 Bit Processor to S1D13706 Interface 11 4 1 Hardware Connections 11 4 2 S1D13706 Hardware Configuration 12 4 3 Register Memory Mapping 12 5 Software 13 6 References 14 6 1 Documents 14 6 2 Document Sources 14 7 Technical Support 15 7 1 EPSON LCD Control...

Page 614: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 615: ...1D13706 Issue Date 01 02 23 X31B G 015 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 9 Table 4 2 CLKI to BCLK Divide Selection 12 Table 4 1 Summary of Power On Reset Configuration Options 12 List of Figures Figure 4 1 Typical Implementation of 8 bit Processor to S1D13706 Interface 11 ...

Page 616: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 617: ...ded to cover all possible implementation but provides a generic example of how such an interface can be accomplished The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document bef...

Page 618: ...6 does not directly support an 8 bit CPU an 8 bit interface can be achieved with minimal external logic Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the S1D13706 only the write read and wait control signals plus the data and address lines need to be inter faced Since the S1D13706 is a 16 bit d...

Page 619: ...s released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Names Generic 2 Comments AB 16 0 A 16 0 DB 15 0 D 15 0 WE1 Byt...

Page 620: ...dress A17 to be connected to the M R line Note If A17 is unavailable on the 8 bit processor an external decode must be used to gen erate the M R signal BHE is the high byte enable for both read and write cycles and connects to the high byte chip select signal Note In an 8 bit environment this signal is driven by inverting address line A0 thus indi cating that odd addresses are to be read write on ...

Page 621: ...e has an active high WAIT signal it must be inverted as well BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO VDD In order to support an 8 bit processor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical imple mentation of an 8 bit processor to S1D1370...

Page 622: ...128K byte block and the 80K byte display buffer occupies the second 128K byte block An external decoder can be used to decode the address lines and generate a chip select for the S1D13706 whenever the selected 128k byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the S1D13706 whenever the S1D...

Page 623: ...he test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE v2 11 2 12 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE v2 11 2 12 display drivers are availab...

Page 624: ...Development Inc S1D13706 Hardware Functional Specification document number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual document number X31B G 004 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Epson Electronics America website http www eea epson com ...

Page 625: ... Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germ...

Page 626: ...Page 16 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to 8 bit Processors X31B G 015 02 Issue Date 01 02 23 THIS PAGE LEFT BLANK ...

Page 627: ...and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered tradema...

Page 628: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 THIS PAGE LEFT BLANK ...

Page 629: ...elect Module 8 3 S1D13706 Host Bus Interface 9 3 1 Host Bus Interface Pin Mapping 9 3 2 Host Bus Interface Signals 10 4 MC68VZ328 to S1D13706 Interface 11 4 1 Hardware Description 11 4 2 S1D13706 Hardware Configuration 12 4 2 1 Register Memory Mapping 13 4 2 2 MC68VZ328 Chip Select and Pin Configuration 13 5 Software 14 6 References 15 6 1 Documents 15 6 2 Document Sources 15 7 Technical Support 1...

Page 630: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 THIS PAGE LEFT BLANK ...

Page 631: ...r S1D13706 Issue Date 01 02 26 X31B G 016 02 List of Tables Table 3 1 Host Bus Interface Pin Mapping 9 Table 4 1 Summary of Power On Reset Configuration Options 12 Table 4 2 CLKI to BCLK Divide Selection 12 Table 4 3 WS Bit Programming 13 List of Figures Figure 4 1 Typical Implementation of MC68VZ328 to S1D13706 Interface 11 ...

Page 632: ...Page 6 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X31B G 016 02 Issue Date 01 02 26 THIS PAGE LEFT BLANK ...

Page 633: ... Memory LCD Controller and the Motorola MC68VZ328 Dragonball VZ microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appre...

Page 634: ... Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus They may be directly connected to the write enable inputs of a typical memory device 2 2 Chip Select Module The MC68VZ328 can generate up to 8 chip select outputs which are organized into four groups A through D Each chip select group has a common base address register and address mas...

Page 635: ...y the S1D13706 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13706 configuration see Section 4 2 S1D13706 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13706 Pin Names ...

Page 636: ...ory or register accesses This signal is generated by the external address decode circuitry For this example M R may be connected to an address line allowing system address A17 to be connected to the M R line WE0 connects to LWE the low data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the low byte of a 16 bit device WE1 connects to UWE the upper data byte...

Page 637: ...328 Chip Select and Pin Configuration on page 13 A single resistor is used to speed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68VZ328 to S1D13706 using the Dragonball host bus interface For further information on the Dragonball Host Bus interface and AC Timing refer to the S1D13706 Hardware Functional Spec...

Page 638: ...or this implementation of a S1D13706 to Motorola MC68VZ328 microprocessor Table 4 1 Summary of Power On Reset Configuration Options S1D13706 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 0 CNF 2 0 110 Dragonball Host Bus Interface CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface Little Endian bus interface CNF5...

Page 639: ...internal registers occupying the first 128K byte block and the 80K byte display buffer located in the second 128K byte block A17 from the MC68VZ328 is used to select between these two 128K byte blocks 4 2 2 MC68VZ328 Chip Select and Pin Configuration The chip select used to map the S1D13706 in this example CSB1 must have its RO Read Only bit set to 0 its BSW Bus Data Width set to 1 for a 16 bit bu...

Page 640: ... available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The Windows CE display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and Windows CE display drivers are availabl...

Page 641: ...www mot com SPS WIRELESS products MC68VZ328 html Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 Evaluation Board User Manual Document Number X31B G 004 xx Epson Research and Development Inc Programming Notes and Examples Document Number X31B G 003 xx 6 2 Document Sources Motorola In...

Page 642: ...el 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax...

Page 643: ...s document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko...

Page 644: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 THIS PAGE LEFT BLANK ...

Page 645: ...26 X31B G 018 02 Table of Contents 1 Introduction 5 2 Package Description 6 3 Routing 7 3 1 Perimeter Pads 7 3 2 Inner Pads 8 4 References 9 4 1 Documents 9 4 2 Document Sources 9 5 Technical Support 10 5 1 EPSON LCD Controllers S1D13706 10 List of Figures Figure 3 1 Example Perimeter Pad Routing 7 Figure 3 2 Example Inner Pad Routing 8 ...

Page 646: ...Page 4 Epson Research and Development Vancouver Design Center S1D13706 Integrating the CFLGA 104 pin Chip Scale Package X31B G 018 02 Issue Date 01 02 26 THIS PAGE LEFT BLANK ...

Page 647: ...r the S1D13706 It includes an overview of the package and provides an example of how to route the pads This application note is updated as appropriate Please check the Epson Electronics America website at www eea epson com or the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any devel opment We appreciate your comments on our ...

Page 648: ...d just below the outermost layer Microvias are blind vias that go down only one layer and connect the outer layer with the microvia specific layer The traces on microvia specific layers are connected to the other layers of the board by standard vias The S1D13706 CSP has the following characteristics reinforced land type footprint 4 reinforced pads land size 1 05mm 042 in diameter 104 pads land siz...

Page 649: ...outing 3 1 Perimeter Pads Perimeter pads of the S1D13706 CSP are usually fanned out on the top layer using 0 004 traces with 0 0045 spaces at the passage between pads The traces are terminated using standard via technology i e 0 025 via with 0 012 hole The following diagram shows an example for perimeter pad routing Figure 3 1 Example Perimeter Pad Routing ...

Page 650: ...54mm 0 010 in diameter and are fanned out with 0 005 traces with 0 005 spaces at the passage between pads All the Vss pins are inner pins and require connection with the microvia specific layer On this layer all the Vss pads are connected together and are fanned out with multiple traces All the traces on the microvia specific layer must be terminated to a standard through hole via for connection t...

Page 651: ...D13706 Issue Date 01 02 26 X31B G 018 02 4 References 4 1 Documents Epson Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx 4 2 Document Sources Epson Electronics America website http www eea epson com Epson Research and Development website http www erd epson com ...

Page 652: ...d Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riess...

Page 653: ...nd use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademar...

Page 654: ...Page 2 Epson Research and Development Vancouver Design Center S1D13706 Interfacing to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 THIS PAGE LEFT BLANK ...

Page 655: ...O Access Overview 8 2 1 3 Variable Latency IO Access Cycles 9 3 S1D13706 Host Bus Interface 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signal Descriptions 12 4 StrongARM SA 1110 to S1D13706 Interface 13 4 1 Hardware Description 13 4 2 S1D13706 Hardware Configuration 14 4 3 StrongARM SA 1110 Register Configuration 15 4 4 Register Memory Mapping 16 5 Software 17 6 References 18 ...

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Page 657: ...ost Bus Interface Pin Mapping 11 Table 4 1 Summary of Power On Reset Configuration Options 14 Table 4 2 CLKI to BCLK Divide Selection 14 Table 4 3 RDFx Parameter Value versus CPU Maximum Frequency 15 List of Figures Figure 2 1 SA 1110 Variable Latency IO Read Cycle 9 Figure 2 2 SA 1110 Variable Latency IO Write Cycle 10 Figure 4 1 Typical Implementation of SA 1110 to S1D13706 Interface 13 ...

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Page 659: ...06 Embedded Memory LCD Controller and the Intel StrongARM SA 1110 Microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We app...

Page 660: ...ese chip selects are individually programmed in the SA 1110 memory configuration registers and can be configured for either a 16 or 32 bit data bus Byte steering is implemented using the four signals nCAS 3 0 Each signal selects a byte on the 32 bit data bus For example nCAS0 selects bits D 7 0 and nCAS3 selects bits D 31 24 For a 16 bit data bus only nCAS 1 0 are used with nCAS0 selecting the low...

Page 661: ...y for data transfer Read data is latched one half memory cycle after the third successful sample on falling edge Then nOE or nWE is deasserted on the next rising edge and the address may change on the subsequent falling edge Prior to a subsequent data cycle nOE or nWE remains deasserted for RDN 1 memory cycles The chip select and byte selects nCAS 1 0 for 16 bit data transfers remain asserted for ...

Page 662: ...to the Intel StrongARM SA 1110 Microprocessor X31B G 019 02 Issue Date 02 06 26 Figure 2 2 illustrates a typical variable latency IO access write cycle on the SA 1110 bus Figure 2 2 SA 1110 Variable Latency IO Write Cycle A 25 0 nCS4 nWE ADDRESS VALID DATA VALID D 31 0 nOE nCAS 3 0 RDY ...

Page 663: ...ric 2 Host Bus Interface is selected by the S1D13706 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on S1D13706 configuration see Section 4 2 S1D13706 Hardware Configu ration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface...

Page 664: ...connected to an address line allowing system address A17 to be connected to the M R line Chip Select CS must be driven low by nCSx where x is the SA 1110 chip select used whenever the S1D13706 is accessed by the SA 1110 WE1 connects to nCAS1 the high byte enable signal from the SA 1110 which in conjunction with the low byte enable signal allows byte steering of read and write oper ations WE0 conne...

Page 665: ... to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to HIO VDD The following diagram shows a typical implementation of the SA 1110 to S1D13706 interface Figure 4 1 Typical Implementation of SA 1110 to S1D13706 Interface WE1 WE0 DB 15 0 WAIT RD CLKI S1D13706 CS RESET AB 16 1 nCAS1 nWE D 15 0 nC...

Page 666: ...onfiguration required for this implementation of a S1D13706 to SA 1110 interface Table 4 1 Summary of Power On Reset Configuration Options S1D13706 Pin Name value on this pin at the rising edge of RESET is used to configure 1 0 1 0 CNF 2 0 100 Generic 2 Host Bus Interface CNF3 GPIO pins as inputs at power on GPIO pins as HR TFT D TFT outputs CNF4 Big Endian bus interface Little Endian bus interfac...

Page 667: ...ld be set to 1 selects 16 bit bus width Parameter RDFx 4 0 should be set according to the maximum desired CPU frequency as indicated in the table below Parameter RDNx 4 0 should be set to 0 minimum command precharge time Parameter RRRx 2 0 should be set to 0 minimum nCSx precharge time The S1D13706 endian mode is set to little endian To program the SA 1110 for little endian set bit 7 of the contro...

Page 668: ... two 128K byte blocks which are selected using A17 from the SA 1110 A17 is connected to the S1D13706 M R pin The internal registers occupy the first 128K bytes block and the 80K byte display buffer occupies the second 128K byte block Each variable latency IO chip select is assigned 128M Bytes of address space Therefore if nCS4 is used the S1D13706 registers will be located at 4000 0000h and the di...

Page 669: ...de is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13706CFG or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13706 test utilities and display drivers are available from your sales...

Page 670: ...n Research and Development Inc S1D13706 Hardware Functional Specification Document Number X31B A 001 xx Epson Research and Development Inc S1D13706 Programming Notes and Examples Document Number X31B G 003 xx Epson Research and Development Inc S5U13706B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X31B G 004 xx 6 2 Document Sources Intel Developers Website http developer intel c...

Page 671: ... 4346 http www epson com hk Taiwan Epson Taiwan Technology Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 140...

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