LX-300
Manual
2.3.9 Interface Circuit
Figure 2-20 shows the parallel interface circuit block diagram. Data from the host
is
latched within the system
by a WOOSTROBE signal. The system
outputs a BUSY signal
automatically to stop the host computer from sending further data. The CPU block reads the data
latched in the gate array block periodically without generating an interrupt.
STSTEM
PARALLEL l/F
I C I
y / / / / y / / / / / / / / /
STROBE
. . . . .
Figure 2-21 shows
is
Figure 2-20. Parallel Interface Block Diagram
the
serial interface circuit block diagram.
serial interface conforms to
data received
the serial 1/0 of the CPU block from the host
via
driver/receiver
Data is
to an
buffer in the svstem from the
block.
Printing starts when a CR code is received or
the input
filled.
SYSTEM (ICI)
TXD
●
DTR
PB3
35‘ P c l
CTS
6.
I
Figure 2-21. Serial Interface Block Diagram
2-17
Summary of Contents for LX-300
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Page 4: ...REVISION SHEET Revision Issue Date Revision Page Rev A April 6 1994 1st issue 4 j v ...
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