REV.-A
This gate array
has an 8-bit parallel l/F circuit and an expanded port function.
Plo
D5
D3
D2
DO
TESTEN
BUSY
A2
ERROR
Al
AO
IN
P20
P21
P22
P23
Figure A-15.
Pin Diagram
—
S
T
B
—
B U S Y —
P
E
—
E R R O R —
—
—
S L I N —
—
I
T
O
—
—
—
—
Parallel
IIF
System
Power
Serial
General
Port
Watch
Dog
Timer
System
Bus
I
— R X D
—
—
T
M
— P 1 O - P 1 3
—
—
—
— T E S T E N B
— D 7 – O
— A 7 – O
—
—
W
R
—
Figure A-16.
Block Diagram
A-1 6
Summary of Contents for LQ-1060
Page 1: ...EPSON TERMINAL PRINTER L Q 8 6 0 1 0 6 0 TECHNICAL MANUAL ...
Page 5: ...REVISION TABLE REVISION DATE ISSUED I CHANGE DOCUMENT I I 1st issue I v ...
Page 68: ...cc o REV A N N n 1 cc b I al cc u co n4 2 1 Figure 2 14 Main Switching 2 21 ...
Page 79: ...REV A Table 2 20 State of Module 1 1 I W stay E H H L H d O s H H 4 2 32 ...
Page 203: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 17 ...
Page 204: ...REV A Fiaure 5 6 MONPS MONPSE Board Voltage Waveforms z L 5 18 ...
Page 205: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 19 ...
Page 248: ...REV A A 3 DRAWINGS 3 J32 J TI g 4 Figure A 27 MONPS Board Component Layout A 34 ...
Page 250: ... 2 1 1 1 1 I A b 2 Ozaz 1202 C O ZZH Z UOEE vu I 1 Figure A 29 MONPS Board Circuit Diagram ...
Page 252: ...L t g Figure A 31 JUNMM Board Component Layout A 38 ...