8-bit Parallel
Circuit
Figure 2-30 shows the 8-bit parallel interface circuit.
Address mapping. for the
is performed by the CPU via the MMU
The gate array
is employed to simplify the control required from the CPU.
●
Refer to Appendix A.1.1.7 for the details of the
CNI
DATAO–7
STROBE
BUSY
ACKNLG
PE
ERROR
/
+5
l\
RM1O
8
R65–72
+5
R76
r
J7
IN
R8”I
AUTOFEEDXT
=
4 AA
AIC
DINO-7 –
STB
BUSY
ACK
PE
ERR
I
I
r’
CPU (4B)
+5
I
1 : IBF ; It become low when STROBE signal changes from high to low.
2 :
ITO ; it become low when
signal changes from high to low.
Figure
8-Bit
Interface Circuit
Figures 2-31 and 2-32 show the processing sequence for these signals and the interface signal timing.
Table 2-22 shows the control signals used between the printer and host computer.
2-35
Summary of Contents for LQ-1060
Page 1: ...EPSON TERMINAL PRINTER L Q 8 6 0 1 0 6 0 TECHNICAL MANUAL ...
Page 5: ...REVISION TABLE REVISION DATE ISSUED I CHANGE DOCUMENT I I 1st issue I v ...
Page 68: ...cc o REV A N N n 1 cc b I al cc u co n4 2 1 Figure 2 14 Main Switching 2 21 ...
Page 79: ...REV A Table 2 20 State of Module 1 1 I W stay E H H L H d O s H H 4 2 32 ...
Page 203: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 17 ...
Page 204: ...REV A Fiaure 5 6 MONPS MONPSE Board Voltage Waveforms z L 5 18 ...
Page 205: ...Figure 5 6 MONPS MONPSE Board Voltage Waveforms 5 19 ...
Page 248: ...REV A A 3 DRAWINGS 3 J32 J TI g 4 Figure A 27 MONPS Board Component Layout A 34 ...
Page 250: ... 2 1 1 1 1 I A b 2 Ozaz 1202 C O ZZH Z UOEE vu I 1 Figure A 29 MONPS Board Circuit Diagram ...
Page 252: ...L t g Figure A 31 JUNMM Board Component Layout A 38 ...