2
6
26
adjustment of R142, generates 10V gate bias to potentiometers R19/R23, each being set for
300mA drain consumption. At the drains of transistors Q5/Q6 microstrip elements in conjunction
with capacitors C37 to C42 and C47 to C52 form output matching structures to efficiently transfer
the amplified signals to hybrid coupler CP4. After in-phase combining, the signal is delivered to
SMA connector J2 which, in conjunction with J4, can be used for tuning and troubleshooting this
particular amplifier stage.
Jumper cable W2 transfers the signal from the intermediate driver to connector J1 of the final stage
where it is divided into equal amplitude components by an in-phase Wilkinson splitter terminated
with resistor R1. The resulting signals are passed to 90
(
hybrid couplers HY1/HY2 where they are
redivided and distributed to input baluns Z1/Z2/Z3/Z4 which transform the unbalanced signals into
the balanced form required by push-pull transistors Q7/Q8/Q9/Q10. After each balun, a series of
parallel capacitors form the input match for each transistor (e.g., C1/C2/C123/C7/C8/C9 for Q7)
with gate bias delivered from variable voltage regulators U7/U8/U9/U10. Using potentiometers R9/
R37/R55/R83, these regulators are set up to provide 10V to transistor bias adjustments R7/R25/
R30/R35/R53/R71/R76/R81, all calibrated to insure that both drains of each transistor conduct
500mA of idle current. Drain current for each side of transistors Q7 through Q10 is provided
directly from the amplifier’s 32V power supply via .05 ohm power resistors R13/R41/R59/R87 and
RF chokes L1/L2/L3/L4/L5/L6/L7/L8. Since only one drain bias resistor is employed for each
transistor, the transistor’s total current is monitored using dc amplifiers U1/U2/U3/U4 across each
bias resistor. At test points TP1/TP2/TP3/TP4, U1 through U4 will generate voltages proportional
to the total drain current of each transistor at a rate of 1V/1A. On the output side of each transistor
is a balanced matching structure composed of tuned lines and parallel capacitors (e.g., C10/C11/
C12/C127/C19/C20 for Q7) terminated in coaxial balun transformers Z5/Z6/Z7/Z8. The amplified
signals from Z5/Z6 are then combined in hybrid coupler HY3, as the signals from Z7/Z8 are
summed in coupler HY4. The two signals now formed in HY3 and HY4 are joined in the Wilkinson
combiner identified by termination resistor R139 at the amplifier’s output. From here the fully
amplified signal exits the 300 Watt Power Amplifier through connector J2.
For the purposes of troubleshooting and alignment, each parallel final amplifier centered on
transistors Q7/Q8/Q9/Q10 can be isolated by utilizing the SMA connectors provided at the input
and output of each circuit. For example, test point connections J3/J7 can be arranged as input and
output connectors for amplifier circuit Q7 by moving coupling capacitors C131/C21 to connect
J3/J7 directly to baluns Z1/Z5 while leaving the connections to hybrid couplers HY1/HY3 open.
The same can be done for amplifier circuit Q8 with C132-J4/C43-J8, for Q9 with C133-J5/C75-J9
and Q10 with C134-J6/C92-J10. To monitor the performance of transistors Q7 through Q10,
transistor fault circuits made up of comparators U6/U5 have been installed to monitor the ISOlation
ports of output hybrid combiners HY3/HY4. During normal transistor operation, the power entering
HY3/HY4 will be relatively balanced, causing very little power to be developed at the ISO port of
each combiner. However, if a transistor fails, the power imbalance at the input of the correspond-
ing hybrid will cause a significant power increase at its ISOlation port. After passing through
attenuator AT1/AT2, this excess power will be detected by diode CR1/CR2, filtered and delivered
as a dc voltage to comparator U6/U5. Under this circumstance, the voltage at pin 5 of U6/U5 will
exceed the reference at pin 6 supplied by potentiometer R103/R114 causing the comparator output
at pin 7 to go high. Normally, when transistors Q7 through Q10 are operating properly, this voltage
will be low. In either case, these amplifier STATUS voltages are sent to the Amplifier Status
Interface board (A3PC1) where they are ORed and forwarded to the transmitter’s Control/Monitor
board (A5PC1).