2
6
3
IF signal passes through a matching pi-attenuator comprised of resistors R35, R36 and R37 before
amplification by U6, U7 and U8. Transformers T5 and T6 again double the signal voltage to
properly drive the gain expansion diodes CR3 and CR4 which compensate for differential gain and
sync compression created in the 500 Watt Power Amplifier (A3).
The variable gain expansion networks, which provide linearity correction, are centered around dual
diodes CR1 through CR4, slope potentiometers R15, R25, R41, R57, unity gain dc amplifiers U9,
U10, U11, threshold potentiometers R21, R30, R47, R55 and ENABLE/BYPASS switch S1. The
threshold (cut-in) potentiometers determine the point on the IF waveform where the correction, or
gain expansion, will occur and the slope potentiometers dictate the amount of correction/expansion
to be used at that breakpoint. With S1 in the ENABLE position, the four diode pairs form nonlinear
circuits where each diode is reverse biased and the amount of reverse bias dictates the point at
which the diode turns on during the positive and negative cycles of the visual IF carrier envelope.
Each diode is biased using voltages established by the threshold potentiometers in conjunction with
dc amplifiers U9, U10, U11 and U12. L4 through L6 and L9 through L12 isolate the IF signal from
the diode threshold biasing circuitry. When the positive and negative peaks of the visual signal
envelope are sufficient to forward bias a diode pair, the pair turns on placing the resistance of its
respective slope potentiometer in parallel with the series arm of its L-pad (R14, R24, R40, R50).
As a result, the attenuation of the visual IF carrier is reduced during this period causing the
waveform to stretch. Slope control R41 is typically used to correct differential gain while R57
primarily adjusts sync amplitude.
With S1 in the BYPASS position, ground is applied to FET switches Q1 and Q2 placing each diode
pair in hard reverse bias preventing conduction throughout the positive and negative cycles of the
IF carrier envelope. Due to the high reverse resistance provided, each diode network essentially
represents a resistive L-pad (R14/R16, R24/R31, R40/R42, R50/R58) with the IF signal attenuated
by a fixed amount in each location. As a result, no linearity correction is provided.
2.2b
IF/Converter:
Schematic Diagram 40404021/Rev 53
t
A2PC1
IF INPUT (J1)
0dBm to
30dBm peak visual
CORRECTOR LOOP Out (J3)
11dBm peak visual typical
CORRECTOR LOOP In (J4)
12dBm peak visual typical
RF OUT
10 to
18dBm
LO INPUT (J5)
+13dBm minimum
Current Draw
42mA @ +15V
31mA @
15V
185mA @ +5V
The IF/Converter performs three tasks in this transmitter. With the first AGC loop it furnishes level
control for the incoming signal from the modulator, upconverts the IF signal to the desired UHF
channel and then controls the transmitter’s output power through a second gain control loop.
The modulator’s IF input, provided at J1, is amplified or attenuated by variable gain amplifier U1.
This integrated circuit, controlled by the output of integrator U4 via switch S1, (U1) can produce
wide variations in gain ranging from +30dB to
10dB. At the output of U1 is coupling capacitor C3
and 2:1 step-down transformer T1 required for proper impedance matching between U1 and in-
phase splitter CP1. At the output of CP1, two equal amplitude IF signals are delivered for differing
applications. The signal at pin CP1-3 is used to provide a reference for the input AGC loop, while