2
6
25
are contained on the Amplifier Status Interface board (PC1). Monitoring the operating temperature
of each 300 Watt Amplifier and the corresponding power supply control is furnished by the Power
Supply/Thermal Interface board PC2.
2.3a
Power Splitter:
Schematic Diagram 10394220/Rev 51
t
A3CP1
Insertion Loss (J1-J2 & J3)
3.25dB
Frequency
470-806MHz
The Power Splitter is a Wilkinson design which divides the UHF signal from the Exciter drawer into
two signals of equal magnitude with 0
(
phase difference. These in-phase signals are used to
individually drive the two parallel 300 Watt UHF Power Amplifier assemblies (A1, A2).
2.3b
300W UHF Power Amplifier:
Schematic Diagram 40394135/Rev 56
t
A3A1, A3A2
Frequency Response
470-806MHz
RF IN (J1)
+18dBm peak visual
RF OUT (J2)
+58dBm peak visual
Gain (J1-J2)
40dB +1/
2dB
Current Draw
22A @ 32V typical
Each 300W UHF Amplifier heat sink assembly consists of a 4 watt input driver stage, a 40 watt
intermediate driver stage and a 300 watt final amplifier, collectively providing approximately 40dB
of signal gain. To insure redundant operation, all amplifier stages utilize parallel transistors. The
input driver stage is built around LDMOS devices Q1/Q3, designed to supply 18dB of gain as
Class A amplifiers. Transistors Q2/Q4 furnish the appropriate bias and current regulation for the
RF devices with potentiometers R6/R7 set to supply 500mA of drain current to each. Capacitors
C3/C4/C5/C6 in conjunction with C50/C53 provide the proper input match for Q1/Q3. Coupling
capacitors C1/C2 bring in out-of-phase, equal amplitude signals from 90
(
hybrid coupler CP1 which
splits the input signal entering the amplifier at connector J1. Attenuator AT1 is selected to insure
that the gains of both 300W Amplifiers are matched within 0.5dB across the band of operation. At
the outputs of Q1/Q3 capacitors C15/C16/C17/C18/C19/C20 are part of microstrip matching
networks that couple the amplified signals into 90
(
hybrid combiner CP2. For maintenance and
troubleshooting purposes, SMA connector J3 is installed at the output of CP2 and connected via
jumper cable to the input of the intermediate driver amplifier.
The incoming signal at connector J4 is again split into equal amplitude, out-of-phase signals by
hybrid coupler CP3 and sent through two input matching networks composed of tuned microstrip
lines and capacitors C21 through C32. RF LDMOS transistors Q5/Q6 form a 40 watt class AB
amplifier featuring 14dB of gain. Both transistors receive drain current directly from the 32V supply
via 0.1 ohm bias resistors R130(A)/R121(D). To effectively measure the current through these
resistors, and therefore through each transistor, dc amplifiers U12/U11 monitor the voltage across
bias resistors R130/R121 producing a voltage at test points TP5/TP6. Each voltage will be
proportional to the drain current of the associated transistor using a ratio of 1V/100mA. Regulated
gate bias for each device is delivered from variable voltage regulator U13 which, through