RELEASED: 10/2/2006
Page 36
COMMUNICATI0NS
HSD SERIES OPERATION AND MAINTENANCE
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3.8 Driver Amplifier Module:
P/N 50524000
Schematic Diagram, 50524002A, D1A4
Gain (J1-J2)
+34dB Typical
Drain of Q1
10.2Vdc @ 360mAdc
Drain of Q2 and Q3
10Vdc @ 1.3Adc
Digital Mode:
RF Input (J1)
0dBm Average Power
RF OUTPUT (J2)
≈
34dBm Average Power
Analog Mode:
Visual IF Input (J1)
≈
+6dBm peak
Aural IF Input (J1)
≈
-7dBm average
VISUAL RF OUTPUT (J2)
≈
+40dBm
AURAL RF OUTPUT (J2)
≈
+27dBm
The HSD driver amplifier is located in the up-converter drawer. The module
provides and end-to-end gain of 33dB and operates class A. The input level to the
module at J2 is 0dBm average power. The first stage of gain is provided by U1
which has a gain of 13dB and is biased with 9 volts at 200ma. The U1 output is
coupled to the second gain stage Q1 through a microstrip network. Q1 has a
variable bias circuit adjusted by R20. The bias adjustment is necessary to
compensate for bias for different devices, and must be re-adjusted if the
replacement of Q1 is required. R20 is adjusted for a voltage of 1.8V measured
across R17 and R18, which creates a nominal drain bias of 10.2 volts at 360ma.
The gain of the Q1 circuit is 11dB. R1 provides gate current limiting and low
frequency stability.
The Q1 output is connected to the 90 degree hybrid splitter CP1 through a printed
micro strip line. The splitter exhibits a throughput loss of 3dB. The network of R5,
R6, and R7 provide a 50 ohm match for the isolation port of the splitter. The two
outputs of CP1 are equal in amplitude but 90 degrees out of phase. The two outputs
feed the circuits of Q2 and Q3 which are identical. The gate bias circuits of Q2 and
Q3 are adjusted by potentiometers R2 and R9 respectively which adjust the drain
currents of Q2 and Q3. To set the correct drain current for Q3, adjust R9 to set the
voltage drop across R12 at 1.95 volts. This sets a drain current of 1.3 amps and a
drain voltage of 10 volts. To set the drain current of Q2, use potentiometer R3 and
set the voltage drop across R11 in the same way.
The outputs of the Q2 and Q3 circuits are then combined in phase by coupler CP2
