RELEASED: 10/2/2006
Page 25
COMMUNICATI0NS
HSD SERIES OPERATION AND MAINTENANCE
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The Linearity Corrector is a two-stage, unity gain circuit which compensates for
nonlinear distortions generated in the transmitter's 12.5 watt Power Amplifier
modules. When properly adjusted, it provides correction to the transmitter’s output
signal for sync amplitude, differential gain and intermodulation.
The variable gain expansion network, which provides linearity correction, is centered
around dual diode CR5, slope potentiometers R18, unity gain dc amplifiers U8 and
threshold potentiometer R58. The threshold (cut-in) potentiometer determines the
point on the IF waveform where the correction, or gain expansion, will occur and the
slope potentiometer dictates the amount of correction/expansion to be used at that
breakpoint. The diode pair forms a nonlinear circuit where each diode is reverse
biased and the amount of reverse bias dictates the point at which the diode turns on
during the positive and negative cycles of the IF carrier envelope. Each diode is
biased using voltages established by the threshold potentiometer in conjunction with
dc amplifier U8. L4 and L5 isolate the diode threshold biasing circuitry from the IF
signal. When the positive and negative peaks of the visual signal envelope are
sufficient to forward bias the diode pair, the pair turns on placing the resistance of its
respective slope potentiometer in parallel with the series arm of its L-pad (R17). As
a result, the attenuation of the IF carrier is reduced during this period causing the
waveform to stretch. Slope control R18 is used to correct for the compression slope
of the output amplifiers.
The output of the Linearity Corrector circuit feeds through a “T” attenuator formed by
R20, R21, and R22. The signal then feeds the output pin diode attenuator (CR6 and
CR7) which is part of the output AGC loop. The output AGC provides power output
stability over a wide operating temperature range. The AGC range is approximately
3dB. The AGC control input at J1 pin 7 (E6) feeds the gate of Q4, a logic level
switching FET which in turn controls analog switch U10. When the AGC is off, the
gate of Q4 is high and the drain is low so pin 2 of the switch is connected to pin 1,
providing a 0 volt drive to U11A which then eliminates control of the pin diode
attenuator, and thereby setting the AGC range to its midpoint.
Conversely, if the gate of Q4 is switched low (AGC on) the switch connects pins 8
and 1, connecting the AGC control circuitry composed of U9 and U11. The AGC
loop action is controlled by the Power Adjust potentiometer R51. U9 is a difference
amplifier which compares the voltage coming from the Detector Module forward
power sample input at J1 pin 6 (E5) and the voltage from the power adjustment at
R51. The forward sample feeds through amplifier U9B which has a gain of 2. The
resultant AGC action is attempting to provide 0 volts at the output of U9A by forcing
the level of the forward sample input to be the same as the reference setting of R51.
Potentiometer R64 (Sample Adjust) sets the operating window of the AGC. To set
the AGC, turn on the AGC and set the Sample Adjust control (R64) for the same
power as the level with the AGC in the off mode.
