Embedian, Inc.
42
SMARC-iMX8MM Computer on Module User’s Manual
v. 1.2
i.MX8M
Mini
processor
and
Qualcomm
Atheros
AR8035
implementation
is
shown
in
the
following
table:
NXP
i.MX8M
Mini
CPU
Qualcomm
AR8035
Net
Names
Note
Ball
Mode
Pin
Name
Pin#
Pin
Name
Gigabit
LAN
AB27
ALT0
ENET_MDIO__
ENET1_MDIO
39
MDIO
ENET_MDIO
Serial
Management
Interface
data
input/output
AC27
ALT0
ENET_MDC__
ENET1_MDC
40
MDC
ENET_MDC
Serial
Management
Interface
clock
AE27
ALT0
ENET_RD0__
ENET1_RGMII_RD0
29
RXD0
RMII_RD0
Bit
0
of
the
4
data
bits
that
are
sent
by
the
transceiver
on
the
receive
path.
AD27
ALT0
ENET_RD1__
ENET1RGMII_RD1
28
RXD1
RMII_RD1
Bit
1
of
the
4
data
bits
that
are
sent
by
the
transceiver
on
the
receive
path.
AD26
ALT0
ENET_RD2__
ENET1_RGMII_RD2
26
RXD2
RMII1_RD2
Bit
2
of
the
4
data
bits
that
are
sent
by
the
transceiver
on
the
receive
path.
AC26
ALT0
ENET_RD3__
ENET1_RGMII_RD3
25
RXD3
RGMII_RD3
Bit
3
of
the
4
data
bits
that
are
sent
by
the
transceiver
on
the
receive
path.
AE26
ALT0
ENET_RXC__
ENET1_RGMII_RXC
31
RX_CLK
RGMII_RXC
Reference
clock
AF27
ALT0
ENET_RX_CTL__
ENET1_RGMII_RX_
CTL
30
RX_DV
RGMII_RX_CTL
Indicates
both
the
receive
data
valid
(RXDV)
and
receive
error
(RXER)
functions
per
the
RGMII
specification.
