Embedian, Inc.
31
SMARC-iMX8MM Computer on Module User’s Manual
v. 1.2
A
24
bit
dual
channel
LVDS
implementation
comprises
10
differential
pairs:
4
pairs
for
odd
pixel
and
control
data;
1
pair
for
the
LVDS
clock
for
the
odd
data;
4
pairs
for
the
even
pixel
data
and
control
data,
and
1
pair
for
the
even
LVDS
clock.
To
use
the
dual
channel
LVDS
mode,
you
need
a
display
supporting
the
dual
channel
LVDS
mode
in
order
to
receive
odd
and
even
pixel
data.
2.1.6.3
Other
LCD
Control
Signals
The
signals
in
the
table
below
support
the
LVDS
LCD
interfaces
(as
these
are
created
from
the
same
i.MX8M
Mini
source).
Edge
Golden
Finder
Signal
Name
Direction
Type
Tolerance
Description
LCD0_VDD_EN
Output
CMOS
1.8V
High
enables
panel
VDD
LCD0_BKLT_EN
Output
CMOS
1.8V
High
enables
panel
backlight
LCD0_BKLT_PWM
Output
CMOS
1.8V
Display
backlight
PWM
control
I2C_LCD_DAT
Bi
‐
Dir
OD
CMOS
1.8V
I2C
data
–
to
read
LCD
display
EDID
EEPROMs
I2C_LCD_CK
Output
CMOS
1.8V
I2C
clock
–
to
read
LCD
display
EDID
EEPROMs
