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Embedian SMARC-iMX8MM, User Manual

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Embedian, Inc. 

21 

SMARC-iMX8MM Computer on Module User’s Manual 

v. 1.2

 

Chapter

 

2

 

Specifications

 

2.1

 

SMARC

‐

iMX8MM

 

General

 

Functions

 

2.1.1.

 

SMARC

‐

iMX8MM

 

Feature

 

Set

   

This

 

section

 

lists

 

the

 

complete

 

feature

 

set

 

supported

 

by

 

the

 

SMARC

‐

iMX8MM

 

module.

 

SMARC

 

Feature

 

Specification

 

SMARC

 

2.0

 

Specification

 

Maximum

 

Number

 

Possible

 

SMARC

‐

iMX8MM

 

Feature

 

Support

 

SMARC

‐

iMX8MM

 

Feature

 

Support

 

Instances

 

LVDS

 

LCD

 

Display

 

Support

 

1

 

Yes

 

1

 

(dual

 

channel)

Note1

 

DP/eDP

 

1

   

No

 

N/A

HDMI

 

Display

 

Support

 

1

 

No

 

 

N/A

 

Serial

 

Camera

 

Support

 

2

 

Yes

 

1

 

(4

‐

lanes)

 

USB

 

Interface

 

6

 

Yes

 

5

 

(1

 

x

 

USB

 

2.0

 

OTG,

 

4

 

x

 

USB

 

2.0)

 

PCIe

 

Interface

 

4

 

Yes

 

1

 

(

 

x1

 

Gen

 

2.0)

 

SATA

 

Interface

 

1

 

No

 

N/A

 

GbE

 

Interface

 

1

 

Yes

 

1

 

2

nd

 

GBE

 

Interface

 

1

 

No

 

N/A

 

SDIO

 

Interface

 

(4bit)

 

1

 

Yes

 

1

   

SPI

 

Interface

 

2

 

Yes

 

2

 

I2S

 

Interface

 

2

 

Yes

 

2

 

I2C

 

Interface

 

6

 

Yes

 

4

 

Serial

 

4

 

Yes

 

4

 

Summary of Contents for SMARC-iMX8MM

Page 1: ...ni Cortex A53 and Cortex M4 24bits dual channel LVDS LCD 4 x COM Ports 1 x SDHC 1 x USB OTG 2 0 4 x USB Host 2 0 1 x 10 100 1000M Gigabit Ethernet 2 x CAN Bus 2 x SPIs 4 x I2Cs 1 x PCIe 2 0 1 x MIPI_C...

Page 2: ...Embedian Inc 2 SMARC iMX8MM Computer on Module User s Manual v 1 2...

Page 3: ...mbedian Inc 3 SMARC iMX8MM Computer on Module User s Manual v 1 2 Revision History Revision Date Changes from Previous Revision 1 0 2020 02 10 Initial Release 1 2 2021 05 18 Fix Typos in this Document...

Page 4: ...anguage or computer language in any form or by any means electronic mechanical photocopying recording or otherwise without the express written permission of EMBEDIAN Trademarks The following lists the...

Page 5: ...aintenance EMBEDIAN will not be responsible for any defects or damages to other products not supplied by EMBEDIAN that are caused by a faulty EMBEDIAN product Technical Support Technicians and enginee...

Page 6: ...MX8MM GENERAL FUNCTIONS 21 2 2 SMARC IMX8MM DEBUG 91 2 3 MECHANICAL SPECIFICATIONS 91 2 4 ELECTRICAL SPECIFICATIONS 107 2 5 ENVIRONMENTAL SPECIFICATIONS 110 CHAPTER 3 CONNECTOR PINOUT 112 3 1 SMARC IM...

Page 7: ...riables and document titles monospaced type Filenames pathnames and code examples Embedian Information Document Updates Please always check the product specific section on the Embedian support website...

Page 8: ...nc 8 SMARC iMX8MM Computer on Module User s Manual v 1 2 Additional Resources Please also refer to the most recent NXP i MX8M Mini processor reference manual and related documentation for additional i...

Page 9: ...ntroduction This Chapter gives background information on the SMARC iMX8MM Section include Features and Functionality Module Variant Differences between Module Variants Block diagram Software Support H...

Page 10: ...h a low profile 314 pin 0 5mm pitch right angle connector this connector is sometimes identified as an 321 pin connector but 7 pins are lost to the key Featuring NXP s i MX8M Mini System on Chip Embed...

Page 11: ...c 11 SMARC iMX8MM Computer on Module User s Manual v 1 2 9 Ubuntu 18 04 and Android Pie 9 0 allow immediate and professional embedded product development with dramatically reduced design risk and time...

Page 12: ...4GB LPDDR4 Networking 1 x 10 100 1000 Mbps Ethernet Display Single channel LVDS LCD 24 bit or dual channel LVDS Expansion 1 x SDHC SDIO 5x USB 2 0 one OTG 1 x PCIe x1 Gen 2 0 USB 4 x USB 2 0 Host 1 x...

Page 13: ...up to 2 x 1 8GHz 3 dual lite core CPU running up to 2 x 1 8GHz No VPU 2 solo core CPU running up to 1 x 1 8GHz 1 solo core CPU running up to 1 x 1 8GHz No VPU 2 2G 2GB LPDDR4 memory 4G 4GB LPDDR4 memo...

Page 14: ...3 Block Diagram The following diagram illustrates the system organization of the SMARC iMX8MM Arrows indicate direction of control and not necessarily signal flow Figure 1 SMARC iMX8MM Block Diagram...

Page 15: ...port BSPs for other operating systems are planned Check with your Embedian contact for the latest BSPs This manual goes into a lot of detail on I O particulars information is provided on exactly how t...

Page 16: ...10 www picmg org SD Specifications Part 1 Physical Layer Simplified Specification Version 3 01 May 18 2010 2010 SD Group and SD Card Association Secure Digital www sdcard org SPI Bus Serial Peripheral...

Page 17: ...ics Standards Association www vesa org 1 5 2 SGET Documents SMARC_Hardware_Specification_V200 version 2 0 June 2nd 2016 SMARC_Hardware_Specification_V1p1 version 1 1 May 29 2014 1 5 3 Embedian Documen...

Page 18: ...7th 2019 rev 2 IMX8MMIEC i MX 8M Mini Applications Processor Datasheet for Industrial Products April 25 2019 rev 0 2 IMX8MMCEC i MX 8M Mini Applications Processor Datasheet for Consumer Products April...

Page 19: ...cessors 1 5 6 NXP Software Documents Linux 4 14 98_2 0 0_ga Android P9 0 0_2 0 0_ga Documentation 1 5 7 Embedian Software Documents Embedian Linux BSP for SMARC iMX8MM Module Embedian Android BSP for...

Page 20: ...on Module User s Manual v 1 2 Specifications This Chapter provides SMARC iMX8MM specifications Section include SMARC iMX8MM General Functions SMARC iMX8MM Debug Mechanical Specifications Electrical Sp...

Page 21: ...aximum Number Possible SMARC iMX8MM Feature Support SMARC iMX8MM Feature Support Instances LVDS LCD Display Support 1 Yes 1 dual channel Note1 DP eDP 1 No N A HDMI Display Support 1 No N A Serial Came...

Page 22: ...8V 1 8V Note 1 Dual channel LVDS interface 2 x 18 bpp OR 2 x 24 bpp up to 1 920 1 200 60 fps at 24 bpp Default configuration is single channel 24 bit To change this configuration users need to send i...

Page 23: ...0 L2 Cache 512KB L2 512KB L2 512KB L2 512KB L2 GPU GCNanoUltra 3D GC320 2D 1 shaders OpenGL ES 2 0 and OpenVG 1 1 GCNanoUltra 3D GC320 2D 1 shaders OpenGL ES 2 0 and OpenVG 1 1 GCNanoUltra 3D GC320 2D...

Page 24: ...up from the onboard eMMC flash first The firmware in eMMC flash will read the BOOT_SEL configuration from the boot selection and boot up the devices from that selected 2 1 5 Clocks A 24 MHz oscillato...

Page 25: ...XP i MX8MM Cortex A53 processor passing through a TI SN65DSI84 MIPI DSI Bridge To FLATLINK LVDS Each channel consists of one clock pair and four data pairs The LVDS signals support the flow of MIPI DS...

Page 26: ...Embedian Inc 26 SMARC iMX8MM Computer on Module User s Manual v 1 2 The following figure shows the LVDS LCD block diagram Figure 2 SMARC iMX8MM LVDS LCD Diagram...

Page 27: ...igured as an 18 bit 24 bit single channel LVDS output or a dual channel LVDS output by accessing TI SN65DSI84 0x18 register via I2C_GP bus The default configuration from software is 24 bit single chan...

Page 28: ...MIPI_DSI_CLK_P H5 DACP MIPI_DSI_CLK A9 ALT0 MIPI_DSI_D0_N__ MIPI_DSI_D0_N J3 DA0N MIPI_DSI_D0 B9 ALT0 MIPI_DSI_D0_P__ MIPI_DSI_D0_P H3 DA0P MIPI_DSI_D0 A10 ALT0 MIPI_DSI_D1_N__ MIPI_DSI_D1_N J4 DA1N M...

Page 29: ...S0_0 eDP0_TX0 DSI0_D0 LVDS0_0 D8 A_Y1P S128 LVDS0_1 eDP0_TX1 DSI0_D1 LVDS0_1 LVDS0 LCD data channel differential pairs 2 D9 A_Y1N S129 LVDS0_1 eDP0_TX1 DSI0_D1 LVDS0_1 E8 A_Y2P S131 LVDS0_2 eDP0_TX2 D...

Page 30: ...eDP1_TX0 DSI1_D0 LVDS1_0 LVDS1 LCD data channel differential pairs 1 A3 B_Y0N S112 LVDS1_0 eDP1_TX0 DSI1_D0 LVDS1_0 B4 B_Y1P S114 LVDS1_1 eDP1_TX1 DSI1_D1 LVDS1_1 LVDS1 LCD data channel differential p...

Page 31: ...LVDS mode in order to receive odd and even pixel data 2 1 6 3 Other LCD Control Signals The signals in the table below support the LVDS LCD interfaces as these are created from the same i MX8M Mini so...

Page 32: ...RXFS__ GPIO4_IO0 S127 LCD0_BKLT_EN LCD_ BKLT_EN High enables panel backlight AF16 ALT5 SAI1_RXC__ GOIO4_IO1 S133 LCD0_VDD_EN LCD_ VDD_EN High enables panel VDD AF8 ALT1 SPDIF_EXT_CLK__ PWM1_OUT S141 L...

Page 33: ...SB 0 4 A Microchip USB2514 is used to expand four USB 2 0 ports from i MX8M Mini USB2 2 0 Host Port Per the SMARC specification the module supports a USB On The Go OTG port capable of functioning eith...

Page 34: ...de Pin Name Pin Pin Name USB0 Port USB 2 0 OTG B22 USB1_DP P60 USB0 USB0 USB0 data pair A22 USB1_DN P61 USB0 USB0 M26 ALT5 NAND_DATA04__ GPIO3_IO10 P62 USB0_EN_OC USB0_EN_OC USB0 power enable over cur...

Page 35: ...VBUS Detect From USB2514 P67 USB1_EN_OC USB1_EN_OC USB1 power enable over current indication signal P69 USB2 USB2 USB_DN1 of USB2514 P70 USB2 USB2 From USB2514 P71 USB2_EN_OC USB2_EN_OC USB2 power ena...

Page 36: ...USB Type C connector a PTN5110 cc logic needs to be added in your carrier board Please refer to i MX8M Mini evaluation board The USB Type C specification describes how the USB device uses pull down pu...

Page 37: ...lled low by Module OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation A 10k pull up is present on the Module to a 3 3V rail The pull up rail may be swit...

Page 38: ...3 _EN_OC low to disable the power delivery to the USBx device 3 The Module floats USB 0 3 _EN_OC to enable power delivery The line is pulled to 3 3V by the Module pull up enabling the Carrier board US...

Page 39: ...n the SMARC USB 0 3 _EN_OC lines Outputs driving the USBx_EN_OC lines are open drain The Carrier board USB power switch if present is enabled by USB 0 3 _EN_OC after a device connection is detected on...

Page 40: ...5 physical layer PHY transceiver with variable I O voltage that is compliant with the IEEE 802 3 2005 standards The AR8035 supports communication with an Ethernet MAC via a standard RGMII interface Th...

Page 41: ...Embedian Inc 41 SMARC iMX8MM Computer on Module User s Manual v 1 2 This is diagrammed below Figure 5 Gigabit Ethernet Connection from i MX8M Mini to Qualcomm Atheros AR8035...

Page 42: ...4 data bits that are sent by the transceiver on the receive path AD27 ALT0 ENET_RD1__ ENET1RGMII_RD1 28 RXD1 RMII_RD1 Bit 1 of the 4 data bits that are sent by the transceiver on the receive path AD26...

Page 43: ...transmits data to the transceiver using this signal AF26 ALT0 ENET_TD1__ ENET1_RGMII_TD1 35 TXD1 RGMII_TD1 The MAC transmits data to the transceiver using this signal AG25 ALT0 ENET_TD2__ ENET1_RGMII...

Page 44: ...ial Transmit Receive Negative Channel 0 P28 GbE_CTREF GBE_CTREF Center tap reference voltage 12 TRXP1 P27 GbE_MDI1 GBE_MDI1 Differential Transmit Receive Positive Channel 1 13 TRXN1 P26 GbE_MDI1 GBE_M...

Page 45: ...k Activity Indication LED Driven low on Link 10 100 or 1000 mbps Blinks on Activity Could be able to sink 24mA or more Carrier LED current 24 LED_10_100 P21 GbE_LINK100 GBE_LINK100 Link Speed Indicati...

Page 46: ...2 to magnetics Media Dependent Interface GBE_MDI3 GBE_MDI3 Bi Dir GBE_MDI Bi directional transmit receive pair 3 to magnetics Media Dependent Interface GBE_100 Output OD CMOS 3 3V Link Speed Indicatio...

Page 47: ...Configuration Halo HFJ11 1G02E Integrated RJ45 8 0o C 70o C HP Auto MDIX UDE RB1 BA6BT9WA Integrated RJ45 8 40o C 85o C HP Auto MDIX Halo TG1G S002NZRL 24 pin SOIC W 8 0o C 70o C HP Auto MDIX For ind...

Page 48: ...processor to the PCI Express port A of the SMARC iMX8MM edge finger These signals support PCI Express Gen 2 0 interfaces at 5 Gb s and are backward compatible to Gen 1 1 interfaces at 2 5 Gb s Diodes...

Page 49: ...interrupt to host PCI Express Port A M27 ALT5 NAND_CE2_B__ GPIO3_IO3 P75 PCIE_A_RST PCIE_A_RST Reset Signal for external devices B21 PCIE_CLK_P P83 PCIE_A_REFCK PCIE_A_REFCK Differential PCI Express R...

Page 50: ...odule Caps is 0402 package 0 1uF PCIE_A_RX PCIE_A_RX Input HCSL PCIe Differential PCIe Link A receive data pair 0 No coupling caps on Module PCIE_A_REFCK PCIE_A_REFCK Output HCSL PCIe Differential PCI...

Page 51: ...provide support for time sensitive signals to the camera Non time sensitive controls such as configuration reset are performed by the ARM platform through I2C interface or GPIO signals The SMARC speci...

Page 52: ...Embedian Inc 52 SMARC iMX8MM Computer on Module User s Manual v 1 2 The following figure shows the serial camera interface block diagram Figure 7 MIPI Serial Camera Interface Block Diagram...

Page 53: ...SI_CLK_N P4 CSI1_CK CSI1_CK CSI1 differential clock inputs B16 ALT0 MIPI_CSI_CLK_P P3 CSI1_CK CSI1_CK A14 ALT0 MIPI_CSI_D0_N P8 CSI1_RX0 CSI1_D0 CSI1 differential data inputs B14 ALT0 MIPI_CSI_D0_P P7...

Page 54: ...ranges NXP i MX8M Mini CPU SMARC iMX8MM Edge Golden Finger Net Names Note Ball Mode Pin Name Pin Pin Name I2C_CAM0 D10 ALT0 I2C2_SCL__ I2C2_SCL S5 CSI0_TX I2C_CAM0_CK I2C_CAM0_CK D9 ALT0 I2C2_SDA__ I2...

Page 55: ...ck I2C_CAM1 I2C_CAM1_DAT Bi Dir OD CMOS 1 8V Serial camera support link I2C data I2C_CAM1_CK Bi Dir OD CMOS 1 8V Serial camera support link I2C clock 2 1 10 2 MIPI Serial Camera In MIPI CSI1 Edge Gold...

Page 56: ...8 bit eMMC support and the other one is used for external SDHC SDIO interface The SMARC iMX8MM module supports one 4 bit SDIO interface per the SMARC 2 0 specification The SDIO interface uses 3 3V sig...

Page 57: ...D2_USDHC2_ DATA1 P40 SDIO_D1 SDIO_D1 SDIO Data 1 V24 ALT0 SD2_DATA2__ SD2_USDHC2_ DATA2 P41 SDIO_D2 SDIO_D2 SDIO Data 2 V23 ALT0 SD2_DATA3__ SD2_USDHC2_ DATA3 P42 SDIO_D3 SDIO_D3 SDIO Data 3 AA27 ALT5...

Page 58: ...are 10k pull up to 3 3V on module 2 1 11 1 SDIO Card 4 bit Interface The Carrier SDIO Card can be selected as the Boot Device See section 4 3 Edge Golden Finder Signal Name Direction Type Tolerance D...

Page 59: ...o chip selects that can connect two SPI slave devices on each channel SPI devices will share the SPI0_DIN SPI0_DO and SPI0_CK pins but each device will have its own chip select pin The chip select sig...

Page 60: ...Embedian Inc 60 SMARC iMX8MM Computer on Module User s Manual v 1 2 The SPI interface is diagramed below Figure 9 SPI Interface Block Diagram...

Page 61: ...ECSPI2_SS0__ GPIO5_IO13 P43 SPI0_CS0 SPI0_CS0 SPI0 Master Chip Select 0 output AG14 ALT5 GPIO1_IO00__ GPIO1_IO0 P31 SPI0_CS1 SPI0_CS1 SPI0 Master Chip Select 1 output E6 ALT0 ECSPI2_SCLK__ ECSPI2_SCLK...

Page 62: ...UART1_RXD__ ECSPI3_SCLK P56 ESPI_CK ESPI_SCLK ESPI Master Clock output F13 ALT1 UART1_TXD__ ECSPI3_MOSI P58 ESPI_IO_0 ESPI_IO_0 ESPI Master Data input input to CPU output from SPI device F15 ALT1 UAR...

Page 63: ...Boot Select Edge Golden Finder Signal Name Direction Type Tolerance Description SPI0_CS0 Output CMOS 1 8V SPI0 Master Chip Select 0 output SPI0_CS1 Output CMOS 1 8V SPI0 Master Chip Select 1 output S...

Page 64: ...ee Section 4 3 Boot Select Edge Golden Finder Signal Name Direction Type Tolerance Description ESPI_CS0 Output CMOS 1 8V ESPI Master Chip Select 0 output ESPI_CS1 Output CMOS 1 8V ESPI Master Chip Sel...

Page 65: ...signals These signals are derived from the Synchronous Audio Interface SAI of the NXP i MX8M Mini processor The Serial Audio Interface SAI implements a synchronous serial bus interface for connecting...

Page 66: ..._LRCK I2S0_LRCK Left Right audio synchronization clock AC22 ALT0 SAI2_TXD0__ SAI2_TX_DATA0 S40 I2S0_SDOUT I2S0_SDOUT Digital audio Output AC24 ALT0 SAI2_RXD0__ SAI2_RX_DATA0 S41 I2S0_SDIN I2S0_SDIN Di...

Page 67: ...ster clock output to Audio codecs I2S0 Signals I2S0_LRCK Bi Dir CMOS 1 8V Left Right audio synchronization clock I2S0_SDOUT Output CMOS 1 8V Digital audio Output I2S0_SDIN Input CMOS 1 8V Digital audi...

Page 68: ...at 1 8V levels The selection of 1 8V compatible transceivers is a bit limited although more are appearing with time Two such devices are the Texas Instruments TRS3253E and the Maxim MAX13235E illustra...

Page 69: ...29 SER0_TX SER0_TX Asynchronous serial port data out AB22 ALT4 SAI2_RXC__ UART1_DCE_RX P130 SER0_RX SER0_RX Asynchronous serial port data in E18 ALT1 UART3_RXD__ UART1_DCE_ CTS_B P131 SER0_RTS SER0_RT...

Page 70: ...1_SCLK__ UART3_DCE_RX P137 SER2_RX SER2_RX Asynchronous serial port data in A7 ALT1 ECSPI2_MOSI__ UART3_DCE_CTS_ B P138 SER2_RTS SER2_RTS Request to Send handshake line for SER2 B6 ALT1 ECSPI2_SCLK__...

Page 71: ...re 2 wire ports data only Edge Golden Finder Signal Name Direction Type Tolerance Description SER 0 3 _TX Output CMOS 1 8V Asynchronous serial port data out SER 0 3 _RX Input CMOS 1 8V Asynchronous se...

Page 72: ...ication PM Power Management LCD Liquid Crystal Display GP General Purpose CAM0 Camera 0 and CAM1 Camera 1 and HDMI SMARC iMX8MM does not have HDMI interface it defines five out of the six I2C buses an...

Page 73: ...S 1 8V I2C_GP I2C3 General purpose use CMOS 1 8V I2C_LCD I2C2 LCD display support to read LCD display EDID EEPROMs for parallel and LVDS LCD General Purpose CMOS 1 8V I2C_CAM0 I2C2 Serial camera 0 Gen...

Page 74: ...I2C3_SCL S48 I2C_GP_CK I2C_GP_CK General purpose I2C bus clock F10 ALT0 I2C3_SDA__ I2C3_SDA S49 I2C_GP_DAT I2C_GP_DAT General purpose I2C bus data I2C_LCD D10 ALT0 I2C2_SCL__ I2C2_SCL S5 S139 I2C_LCD...

Page 75: ...PCIe Gen 1 2 3 Clock Generator 0x68 0xD1 0xD0 Clock Generator for PCIe Lane A 2 ROHM BD71847MWV E2 PMIC 0x4B 0x01 0x00 PMIC 3 Seiko S 35390A Real time clock IC 0x30 0x61 0x60 Real Time Clock I2C_GP 1...

Page 76: ...th a high level of security The SMARC iMX8MM module implements two CAN bus interfaces from Microchip MCP2515 SPI to CAN interface IC The SPI bus used to interface with MCP2515 CAN controller is SPI0 T...

Page 77: ...Embedian Inc 77 SMARC iMX8MM Computer on Module User s Manual v 1 2 The following figure shows the CAN bus block diagram Figure 11 SMARC iMX8MM CAN Bus Diagram...

Page 78: ...is shown in the following table NXP i MX8M Mini CPU Microchip MCP2515T Net Names Note Ball Mode Pin Name Pin Pin Name F15 ALT1 UART2_RXD__ ECSPI3_MISO 15 SO ESPI_CAN_SO F13 ALT1 UART1_TXD__ ECSPI3_MO...

Page 79: ...s shown in the following table NXP i MX8M Mini CPU Microchip MCP2515T Net Names Note Ball Mode Pin Name Pin Pin Name F15 ALT1 UART2_RXD__ ECSPI3_MISO 15 SO ESPI_CAN_SO F13 ALT1 UART1_TXD__ ECSPI3_MOSI...

Page 80: ...gnaling should be supported on the Module GPIO8 P116 pin This is an active low input to the Module from the CAN bus transceiver CAN1 bus error condition signaling should be supported on the Module GPI...

Page 81: ...al Name Direction Type Tolerance Description CAN0_TX Output CMOS 1 8V CAN0 Transmit output CAN0_RX Input CMOS 1 8V CAN0 Receive input 2 1 16 5 CAN1 BUS Signals Edge Golden Finder Signal Name Direction...

Page 82: ...Specific alternate functions are assigned to some GPIOs such as PWM Tachometer capability Camera support CAN Error Signaling and HD Audio reset All pins are capable of bi directional operation A defa...

Page 83: ...P110 GPIO2 CAM0_RST GPIO2 Camera 0 Reset active low output AD18 ALT5 SAI5_RXD0__ GPIO3_IO21 P111 GPIO3 CAM1_RST GPIO3 Camera 1 Reset active low output AC14 ALT5 SAI5_RXD1__ GPIO3_IO22 P112 GPIO4 HDA_...

Page 84: ...he interrupt characteristics edge or level sensitivity polarity are generally configurable in the i MX8M Mini register set Edge Golden Finder Signal Name Preferre d Directio n Type Tolerance Descripti...

Page 85: ...h the standard Linux Watchdog API A description of the API is available following the link below http www kernel org doc Documentation watchdog watchdog api txt WDT signals are exposed on the SMARC go...

Page 86: ...n and pin out Figure 12 JTAG Connector Location and Pinout JTAG functions for CPU debug and test are implemented on separate small form factor connector CN3 JST SM10B SRSS TB 1mm pitch R A SMD Header...

Page 87: ...G 1 VDD_33A Power JTAG I O Voltage sourced by Module C27 ATL0 JTAG_TRST_B 2 nTRST I JTAG Reset active low F27 ALT0 JTAG_TMS 3 TMS I JTAG mode select E26 ALT0 JTAG_TDO 4 TDO O JTAG data out E27 ALT0 JT...

Page 88: ...rial EEPROM is placed at I2C slave addresses A2 A1 A0 set to 0 I2C slave address 50 hex 7 bit address format or A0 A1 hex 8 bit format for I2C EEPROMs address bits A6 A5 A4 A3 are set to binary 0101 c...

Page 89: ...n Module with Quad Lite Core and 2GB LPDDR4 Configuration SM8MM54G Embedian SMARC iMX8MM Computer on Module with Quad Lite Core and 4GB LPDDR4 Configuration SM8MM42G Embedian SMARC iMX8MM Computer on...

Page 90: ...on YY 2 digit year of production MS Module Serial Number D1 Q1 D2 Q2 UC SC CPU Core and DDR Configuration Variants nnnn incrementing board number Configuration Option 32 Codes to show the configuratio...

Page 91: ...ation Carrier The default baud rate setting is 115 200 8N1 SER3 pin out of the SMARC iMX8MM is shown below NXP i MX8M Mini CPU SMARC iMX8MM Edge Golden Finger Net Names Notes mode Pin Name Pin Pin Nam...

Page 92: ...without PCB complied with SMARC specification defines as 1 3mm as the maximum 2 3 4 Mechanical Drawings The mechanical information is shown in Figure 13 SMARC iMX8MM Mechanical Drawings Top View and F...

Page 93: ...omputer on Module User s Manual v 1 2 Figure 14 SMARC iMX8MM Mechanical Drawings Bottom View The figure on the following page details the 82mm x 50mm Module mechanical attributes including the pin num...

Page 94: ...Embedian Inc 94 SMARC iMX8MM Computer on Module User s Manual v 1 2 Figure 15 SMARC iMX8MM Module Mechanical Outline...

Page 95: ...nc 95 SMARC iMX8MM Computer on Module User s Manual v 1 2 Top side major component IC and Connector information is shown in Figure 16 SMARC iMX8MM Top side components Figure 16 SMARC iMX8MM Top Side C...

Page 96: ...6 SMARC iMX8MM Computer on Module User s Manual v 1 2 Bottom side major component IC and Connector information is shown in Figure 17 SMARC iMX8MM Bottom side components Figure 17 SMARC iMX8MM Bottom S...

Page 97: ...ack height Carrier board connector is used there shall not be components on the Carrier board Top side in the Module region Additionally when 1 5mm stack height connectors are used there should not be...

Page 98: ...3 5 Carrier Board Connector PCB Footprint Figure 19 Carrier Board Connector PCB Footprint Note The hole diameter for the 4 holes 82mm x 50mm Module or 7 holes 82mm x 80mm Module depends on the spacer...

Page 99: ...7 Carrier Board Standoffs Figure 20 Screw Fixation Standoffs secured to the Carrier board are expected The standoffs are to be used with M2 5 hardware Most implementations will use Carrier board stan...

Page 100: ...custom part with 1 5mm standoff length M2 5 internal thread and 5 56mm standoff OD is available from PEM The Carrier PCB requires a 4 22mm hole and 6 2mm pad to accept these parts Other vendors such a...

Page 101: ...5mm 4 3mm Flash Std Black Foxconn AS0B821 S43N H 1 5mm 4 3mm Flash Std Ivory Foxconn AS0B826 S43B H 1 5mm 4 3mm 10 u in Std Black Foxconn AS0B826 S43N H 1 5mm 4 3mm 10 u in Std Ivory Lotes AAA MXM 008...

Page 102: ...5 2mm Flash Std Tan Speedtech B35P101 02122 H 2 76mm 5 2mm 10 u in Std Black Speedtech B35P101 02022 H 2 76mm 5 2mm 10 u in Std Tan Speedtech B35P101 02123 H 2 76mm 5 2mm 15 u in Std Black Speedtech B...

Page 103: ...these pins to allow more signal pins Footprint and pin numbering information for application of this 314 pin connector to SMARC is given in the sections below 2 3 9 Module Cooling Solution Heat Spread...

Page 104: ...thickness details of the TIM vary from design to design The two holes immediately adjacent to the TIM serve to secure the PCB in the SOC area and compress the TIM The four interior holes that are fur...

Page 105: ...Computer on Module User s Manual v 1 2 Dimensions in the figure above are in millimeters TIM stands for Thermal Interface Material The TIM takes up the small gap between the SOC top and the Module fac...

Page 106: ...ate to be flush with a secondary heat sink Hole size depends on standoffs used Standoff diameter must be compatible with SMARC Module mounting hole pad and hole size 6 0mm pads 2 7mm holes on the Modu...

Page 107: ...provided through the VDD_RTC pin from the carrier board This connection provides back up power to the module PMIC The RTC is powered via the primary system 3 3V supply during normal operation and via...

Page 108: ...es 2 4 6 Power Consumption The power consumption values listed in this document were measured under a controlled environment The hardware used for testing includes an SMARC iMX8MM module carrier board...

Page 109: ...Note With the linux stress tool we stressed the CPU to maximum frequency The table below provides additional information about the different variants offered by the SMARC iMX8MM SMARC Part Number Desk...

Page 110: ...o 80 C air temperature without a passive heat sink arrangement Industrial temperature 40o C 85o C is also available with different part number SMARC iMX8MM X XX I 2 5 2 Humidity Operating 10 to 90 RH...

Page 111: ...n Inc 111 SMARC iMX8MM Computer on Module User s Manual v 1 2 Connector PinOut This Chapter gives detail pinout of SMARC iMX8MM golden finger edge connector Section include SMARC iMX8MM Connector Pin...

Page 112: ...key 4 on the primary side and 3 on secondary side The Secondary Bottom side faces the Carrier board when a normal or standard Carrier connector is used The SMARC iMX8MM module pins are deliberately n...

Page 113: ...ication The NXP i MX8M Mini CPU column shows the connection of the CPU signals on the module The format of this column is Ball Mode Signal Name where Signal Name is the chip where the signals are conn...

Page 114: ...fferential data inputs 0 positive P8 CSI1_RX0 A14 MIPI_CSI_D0_N I CSI1 differential data input 0 negative P9 GND P Ground P10 CSI1_RX1 B15 MIPI_CSI_D1_P I CSI1 differential data input 1 positive P11 C...

Page 115: ...INK100 O OD Link Speed Indication LED for 100Mbps Could be able to sink 24mA or more Carrier LED current P22 GbE0_LINK1000 O OD Link Speed Indication LED for 1000Mbps Could be able to sink 24mA or mor...

Page 116: ...ferential Transmit Receive Negative Channel 1 P27 GbE0_MDI1 AIO Qualcomm AR8035 Differential Transmit Receive Positive Channel 1 P28 GbE0_CTREF O Qualcomm AR8035 Center tap reference voltage for GBE C...

Page 117: ...P34 SDIO_CMD W24 ALT0 SD2_CMD__ SD2_CMD IO Command Line P35 SDIO_CD AA26 ALT5 SD2_CD__ GPIO2_IO12 I Card Detect P36 SDIO_CK W23 ALT0 SD2_CLK__ SD2_USDHC2_ CLK O Clock P37 SDIO_PWR_EN AB26 ALT5 SD2_RES...

Page 118: ...output P44 SPI0_CK E6 ALT0 ECSPI2_SCLK__ ECSPI2_SCLK O SPI0 Master Clock output P45 SPI0_DIN A8 ALT0 ECSPI2_MISO__ ECSPI2_MISO I SPI0 Master Data input input to CPU output from SPI device P46 SPI0_DO...

Page 119: ...Clock output P57 ESPI_IO_1 F15 ALT1 UART2_RXD__ ECSPI3_MISO I SPI1 Master Data input input to CPU output from SPI device P58 ESPI1_IO_0 F13 ALT1 UART1_TXD__ ECSPI3_MOSI O SPI1 Master Data output outpu...

Page 120: ..._IO10__ USB1_ID I USB OTG ID input active high P65 USB1 IO Differential USB1 data pair from USB2514 P66 USB1 IO Differential USB1 data pair from USB2514 P67 USB1_EN_OC From USB2514 IO OD Pulled low by...

Page 121: ...le OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation If this signal is used a pull up is required on the Carrier P72 RSVD Not used P73 RSVD Not used P7...

Page 122: ...D_CE2_B__ GPIO3_IO3 O Reset Signal for external devices P76 USB4_EN_OC From USB2514 Pulled low by Module OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situat...

Page 123: ...es A P84 PCIE_A_REFCK from PI6CFGL201BZDIE O Differential PCI Express Reference Clock Signals for Lanes A P85 GND P P86 PCIE_A_RX B19 PCIE_RXN_P I Differential PCIe Link A receive data pair 0 P87 PCIE...

Page 124: ...nual v 1 2 SMARC Edge Finger NXP i MX8M Mini CPU Type Description Pin Pin Name Ball Mode Signal Name P92 HDMI_D2 DP1_LANE0 Not used P93 HDMI_D2 DP1_LANE0 Not used P94 GND P Ground P95 HDMI_D1 DP1_LANE...

Page 125: ...Pin Pin Name Ball Mode Signal Name P98 HDMI_D0 DP1_LANE2 Not used P99 HDMI_D0 DP1_LANE2 Not used P100 GND P Ground P101 HDMI_CK DP1_LANE3 Not used P102 HDMI_CK DP1_LANE3 Not used P103 GND P Ground P10...

Page 126: ...XD0__ GPIO3_IO21 IO Camera 1 Reset active low output P112 GPIO4 HDA_RST AC14 ALT5 SAI5_RXD1__ GPIO3_IO22 IO HD Audio Reset active low output P113 GPIO5 PWM_OUT AF6 ALT5 SPDIF_TX__ GPIO5_IO3 IO PWM out...

Page 127: ...anagement I2C bus data P123 BOOT_SEL0 AF12 ALT0 GPIO1_IO05__ GPIO1_IO5 I SYSBOOT and Line De multiplexer Logic Pulled up on Module Driven by OD part on Carrier P124 BOOT_SEL1 AG11 ALT0 GPIO1_IO06__ GP...

Page 128: ...w level sensitive It is de bounced on the Module Pulled up on Module Driven by OD part on Carrier P129 SER0_TX AC19 ALT4 SAI2_RXFS__ UART1_DCE_TX O Asynchronous serial port data out P130 SER0_RX AB22...

Page 129: ...1 ECSPI2_MOSI__ UART3_DCE_CTS_ B Request to Send handshake line for SER2 P139 SER2_CTS B6 ALT1 ECSPI2_SCLK__ UART3_DCE_RTS_ B Clear to Send handshake line for SER2 P140 SER3_TX AG6 ALT4 SAI3_TXC__ UAR...

Page 130: ...X8M Mini CPU Type Description Pin Pin Name Ball Mode Signal Name P147 VDD_IN P Power in P148 VDD_IN P Power in P149 VDD_IN P Power in P150 VDD_IN P Power in P151 VDD_IN P Power in P152 VDD_IN P Power...

Page 131: ...OD Camera1 I2C bus data S3 GND P Ground S4 RSVD Not used S5 CSI0_TX I2C_CAM0_CK D10 ALT0 I2C2_SCL__ I2C2_SCL IO OD Camera0 I2C bus clock S6 CAM_MCK AC9 ALT6 GPIO1_IO14__ CCMSRCGPCMIX _CLKO1 O Master...

Page 132: ...GbE1_MDI0 Not used S19 GbE1_LINK100 Not used S20 GbE1_MDI1 Not used S21 GbE1_MDI1 Not used S22 GbE1_LINK1000 Not used S23 GbE1_MDI2 Not used S24 GbE1_MDI2 Not used S25 GND P Ground S26 GbE1_MDI3 Not...

Page 133: ...AUDIO_MCK AD19 ALT0 SAI2_MCLK__ SAI2_MCLK O Master clock output to Audio codecs S39 I2S0_LRCK AD23 ALT0 SAI2_TXFS__ SAI2_TX_SYNC IO Left Right audio synchronization clock S40 I2S0_SDOUT AC22 ALT0 SAI...

Page 134: ...ral purpose I2C bus clock S50 HDA_SYNC I2S2_LRCK AG8 ALT0 SAI3_RXFS__ SAI3_RX_SYNC IO Left Right audio synchronization clock S51 HDA_SDO I2S2_SDOUT AF6 ALT0 SAI3_TXD__ SAI3_TX_DATA0 O Digital audio Ou...

Page 135: ...ame S62 USB3_SSTX Not used S63 USB3_SSTX Not used S64 GND P Ground S65 USB3_SSRX Not used S66 USB3_SSRX Not used S67 GND P Ground S68 USB3 Differential USB3 data pair from USB2514 S69 USB3 Differentia...

Page 136: ...Name Ball Mode Signal Name S76 PCIE_B_RST Not used S77 PCIE_C_RST Not used S78 PCIE_C_RX Not used S79 PCIE_C_RX Not used S80 GND P Ground S81 PCIE_C_TX Not used S82 PCIE_C_TX Not used S83 GND P Ground...

Page 137: ...PCIE_B_TX Not used S92 GND P Ground S93 DP0_LANE0 Not used S94 DP0_LANE0 Not used S95 DP0_AUX_SEL Not used S96 DP0_LANE1 Not used S97 DP0_LANE1 Not used S98 DP0_HPD Not used S99 DP0_LANE2 Not used S1...

Page 138: ..._0 eDP1_TX0 DSI1_D0 AIO LVDS1 LCD data channel differential pairs 1 S112 LVDS1_0 eDP1_TX0 DSI1_D0 AIO LVDS1 LCD data channel differential pairs 1 S113 eDP1_HPD Not used S114 LVDS1_1 eDP1_TX1 DSI1_D1 A...

Page 139: ...ifferential pairs 4 S122 LCD1_BKLT_ PWM Not used S123 RSVD Not used S124 GND P Ground S125 LVDS0_0 eDP0_TX0 DSI0_D0 AIO LVDS0 LCD data channel differential pairs 1 S126 LVDS0_0 eDP0_TX0 DSI0_D0 AIO LV...

Page 140: ...eDP0_TX2 DSI0_D2 AIO LVDS0 LCD data channel differential pairs 3 S133 LCD_VDD_EN AF16 ALT5 SAI1_RXC__ GOIO4_IO1 O High enables panel VDD S134 LVDS0_CK eDP0_AUX DSI0_CLK O LVDS0 LCD differential clock...

Page 141: ...S140 I2C_LCD_DAT D9 ATL0 I2C2_SDA__ I2C2_SDA IO OD LCD display I2C bus clock S141 LCD_BKLT_PWM AF8 ALT1 SPDIF_EXT_CLK__ PWM1_OUT O Display backlight PWM control S142 RSVD Not used S143 GND P Ground S1...

Page 142: ...indication to Module Low indicates lid closure which system may use to initiate a sleep state Carrier to float the line in in active state Active low level sensitive Should be de bounced on the Modul...

Page 143: ...enabled while this signal is held low by the Carrier Pulled up on Module Driven by OD part on Carrier S151 CHARGING AF14 ALT0 GPIO1_IO01__ GPIO1_IO1 I Held low by Carrier if DC input for battery char...

Page 144: ...ts should not be powered up until the Module asserts the CARRIER_PWR_ON signal S155 FORCE_RECOV I Pulled up on Module Driven by OD part on Carrier S156 BATLOW AG10 ALT0 GPIO1_IO08__ GPIO1_IO8 I Batter...

Page 145: ...trol Signals between SMARC Module and Carrier This Chapter points out the handshaking rule between SMARC module and carrier Section include SMARC iMX8MM Module Power Power Signals Power Flow and Contr...

Page 146: ...low these rules or it might not boot up Some pull up and pull down also need to be cared to make all functions work 4 1 SMARC iMX8MM Module Power 4 1 1 Input Voltage Main Power Rail The allowable Modu...

Page 147: ...if used on Carrier shall be protected against charging by a Carrier Schottky diode The diode is placed in series with the positive battery terminal The diode anode is on the battery side and the catho...

Page 148: ...gnal of the carrier board The module will not boot up till the module power is ready because the carrier board hasn t released the reset signal yet The sequence is as follows Module Power Ready CARRIE...

Page 149: ...system is not battery powered only 2 SMARC Module power domain 3 Carrier Circuits power domain The Battery Charger domain includes circuits that are active whenever either charger input power and or b...

Page 150: ...to 5 25V I2C_PM CARRIER_PWR_ON MODULE CARRIER INTERFACE FET Isolation Carrier Power Supplies should not Come up before assertion of CARRIER_PWR_ON Additional power enables may be implemented by the s...

Page 151: ...154 P155 P156 VDD_IN I PWR 3 0V 5 25V1 Main power supply input for the module P2 S3 P9 S10 P12 S13 P15 S16 P18 S25 P32 S34 P38 S47 P47 P50 P53 P59 S61 S64 S67 P68 S70 S73 P79 S80 P82 S83 P85 S86 P88 S...

Page 152: ...dge Finger I O Type Power Rail Description Pin Pin Name S150 VIN_PWR_BAD I CMOS VDD_IN Power bad indication from Carrier board S154 CARRIER_PWR_O N O CMOS VDD_IO Signal to inform Carrier board circuit...

Page 153: ...OW I CMOS VDD_IO Battery low indication to Module Carrier to float the line in in active state Pulled up on Module Driven by OD part on Carrier S154 CARRIER_PWR_ON O CMOS VDD_IO Signal to inform Carri...

Page 154: ...eep indicator from Carrier board May be sourced from user Sleep button or Carrier logic Carrier to float the line in in active state Active low level sensitive Should be de bounced on the Module Pulle...

Page 155: ...de restore or at factory default where the firmware in eMMC flash is empty or at development stage that the firmware in eMMC needs to be modified users will need an alternative way to boot up from SD...

Page 156: ...nc 156 SMARC iMX8MM Computer on Module User s Manual v 1 2 4 3 Power Flow and Control Signals Block Diagram Following figures shows the power flow and control signals block diagram Figure 26 Power Blo...

Page 157: ...on the carrier The main body of carrier board circuits will not be powered until the module asserts the CARRIER_PWR_ON signal being correct Module hardware will assert CARRIER_PWR_ON when all power su...

Page 158: ...t the CPU and peripherals are not running Only the PMIC is running Carrier board provides power for module the peripheral supplies are not available SUS Suspend System is suspended and waits for wakeu...

Page 159: ...ts the carrier board to switch of the power rails for the peripherals The module can be brought back to the running mode in two ways The module main voltage rail VDD_IN can be removed and applied agai...

Page 160: ...ule will continue to assert signal RESET_OUT after the release of CARRIER_PWR_ON for a period sufficient time at least 10ms to allow carrier power circuits that the peripheral supplies need to ramp up...

Page 161: ...is allows the operating system to take care of any housekeeping e g bringing mass storage devices to a controlled halt Some operating system may not provide the shutdown function As it is not permitte...

Page 162: ...Embedian Inc 162 SMARC iMX8MM Computer on Module User s Manual v 1 2 Figure 29 Shutdown Sequence...

Page 163: ...output RESET_OUT are asserted as long as RESET_IN is asserted If the reset input RESET_IN is de asserted the internal reset and the RESET_OUT will remain low for at least 1ms until they are also de as...

Page 164: ...MI_CTRL_DAT 1 5k pull up to 1 8V Carrier pull up required HDMI_CTRL_CK 1 5k pull up to 1 8V Carrier pull up required PCIE_ A B _TX 0 2uF Capacitor PCIE_ A B _TX 0 2uF Capacitor I2C_PM_DAT 2 2K pull up...

Page 165: ...rmination Notes USB 0 4 _EN_OC 10K pull up to 3 3V or a switched 3 3V on the Module x is 0 or 1 Switched 3 3V if a USB channel is not used then the USBx_EN_OC pull up rail may be held at GND to preven...

Page 166: ...econdary side center tap terminations appropriate for Gigabit Ethernet implementations GBE_LINK GBE status LED sinks If used current limiting resistors and diodes to pulled to a positive supply rail T...

Page 167: ...s required on the Carrier The pull ups may be part of an integrated HDMI ESD protection and control line level shift device such as the Texas Instruments TPD12S016 If discrete Carrier pull ups are use...

Page 168: ...P1_AUX_SEL Carrier DP1_AUX_SEL should be connected to pin 13 of the DisplayPort connector to enable a dual mode DisplayPort interface DP1_LANE 0 3 DP1_LANE 0 3 DC blocking capacitors shall be placed o...

Page 169: ...BOOT_SELx pins are weakly pulled up on the Module and the pin states decoded by module logic The Carrier shall either leave the Module pin Not Connected Float in the table below or shall pull the pin...

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