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Intel G41 Series User's Manual
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CPU Ration Control
Allows you to adjust the ratio between CPU Core Clock and FSB Frequency.
•
C1E Support
Allows you to enable or disable Enhanced Halt State support.
•
Hardware Prefetcher
This should be enabled in order to enable or disable the Hardware Prefetcher Disable Feature.
•
Adjacent Cache Line Prefetch
This should be enabled in order to enable or disable the Adjacent Cache Line Prefetch Disable
Feature.
•
Max CPUID Value Limit
Setting this item to [Enabled] allows legacy operating systems to boot even without support
for CPUs with extended CPUID functions.
•
CPU TM function
This functio enables the overheated CPU to throttle the clock speed to cool down.
•
Execute-Disable Bit Capability
Allows you to enable or disable the No-Execution Page Protection Technology. Setting this
item to [Disable] forces the XD feature flag to always return to zero(0).
•
Core Multi-Processing
When disabled, disable one execution core of each CPU die.
•
PECI
When enabled, enables PECI interface.
•
Intel(R) SpeedStep(tm) tech
When set to [Disabld], the CPU runs at its default speed. When set to [Enabled], the CPU
speed is controlled by the operating system.
BIOS SETUP UTILITY
Advanced
Configure advanced CPU settings
Module Version: 3F.0E
Control CPU Ratio.
←
Select Screen
↑
↓
Select Item
+- Change Option
F1 General Help
F10 Save and Exit
ESC Exit
Manufacturer:Intel
Intel(R) Core(TM)2 Duo CPU E4500 @ 2.20GHz
Frequency :2.21GHz
FSB Speed :800MHz
Cache L1 :64 KB
Cache L2 :2048 KB
Ratio Status:Unlocked (Min:06, Max:11)
Ratio Actual Value:11
CPU Ratio Control
C1E Support
Hardware Prefetcher
Adjacent Cache Line Prefetch
Max CPUID Value Limit
CPU TM function:
Execute-Disable Bit Capability
Core Multi-Processing
PECI
Inter(R) SpeedStep(tm) tech
[Auto]
[Disabled]
[Enabled]
[Enabled]
[Disabled]
[Enabled]
[Enabled]
[Enabled]
[Enabled]
[Disabled]
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
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CPU Configuration
This items in this menu show the CPU-related information that the BIOS automatically detects.