APPENDIX A: Registers for PCIe8g3 S5
Registers, Port: Port 4 (QSFP/+)
EDT, Inc.
2017 January 04
43
Registers, Port: Port 4 (QSFP/+)
0x840010–0x840098 BAR1 Memory-Mapped
0x840010 Synchronization Control
0x840014 Frame Count Control [Reserved]
0x840060 Detailed Port Status
Access / Notes:
32-bit read-write / STRATIX5_REGXL8(STRATIX5_PSYNC_CTRL, 4)
Bit
Access
Name
Description
31–16
–
–
Reserved.
15
RW
STRATIX5_
TXTRIG_ARM
Set to arm transmit trigger.
14
–
–
Reserved.
13–12
RW
[no name]
Select when DDR3 FIFO transmit will start:
0 = ignore
1 = when FIFO is 50% full
2 = when FIFO is 75% full
3 = when FIFO is 100% full
The transmit logic waits to transmit until the selected threshold is reached.
11–10
–
–
Reserved.
9–8
RW
[no name]
Select transmit trigger source:
0 = external
1 = internal
7
RW
STRATIX5_
RXTRIG_ARM
Set to arm receive trigger.
6–3
–
–
Reserved.
2
RW
[no name]
Set to disable wait for frame receive trigger mode.
1–0
RW
[no name]
Select receive trigger source:
0 = external
1 = internal
Access / Notes:
32-bit read-only / STRATIX5_REGXL8(STRATIX5_PORT_STAT2, 4)
Bit
Access
Name
Description
31–8
–
–
Reserved.
7
R only
[no name]
Lane 3 transceiver clock and data recovery (CDR) is locked to data.
6
R only
[no name]
Lane 3 transceiver clock and data recovery (CDR) is locked to reference clock.
5
R only
[no name]
Lane 2 transceiver clock and data recovery (CDR) is locked to data.
4
R only
[no name]
Lane 2 transceiver clock and data recovery (CDR) is locked to reference clock.
