PCIe8g3 S5 Family
Initialization and Setup
EDT, Inc.
2017 January 04
13
Initialization and Setup
PCIe8g3 S5 boards can be initialized and set up with the
fourp
utility. The recommended sequence is:
1.
Initialize the DDR3 memory and set up the data path.
2.
Initialize the ports as needed.
NOTE
Some setup (such as of the memory and data path) affects all channels, so implement setup with caution.
Initializing Memory and Data Path
To prepare for DMA, the data path must be initialized. Doing so includes setting the data path direction, determining
whether data will be directed to DMA, and verifying that the DDR3 memory PHY has been initialized.
In the default FPGA configuration file provided with your S5 board, the two DDR3 memory banks are divided into two
logical memory banks. In register
0x000010 Data Path and Memory Control
, when port 0, 1, 2, or 3 is set, each port
thus set is assigned a logical memory bank; when port 4 is set, then the four logical memory banks are combined into
a single logical bank. In the same register, the latter result can be achieved with the
fourp
utility by entering...
fourp -rm -p 0 -D -rx
...where the flags have the following effects...
•
The
-rm
flag resets the DDR3 PHY.
•
The
-p 0
flag sets the memory for ports 0, 1, 2, and 3.
•
The
-D
flag sets the data path for DMA.
•
The
-rx
flag sets the data path for receiving data.
NOTE
The
-D
flag always should be used with either the
-rx
or the
-tx
flag (
-rx
and
-tx
are mutually exclusive)
and will affect all ports.
Initializing Ports
Each port can be set up and used independently by using the
fourp
utility and adding the flags...
-p
x
// to determine which port is configured;
-R
x
// to determine which rate is set.
For example, you could enter these three commands, in any sequence...
fourp -p 0 -R stm64
fourp -p 1 -R otu2f
fourp -p 2 -R stm1
...in order to set port 0 to STM64, port 1 to OTU2f, and port 2 to STM1.
NOTE
When you specify a rate, the
fourp
utility does not verify whether a port’s transceiver can support that rate.
Therefore, you must be aware of which transceiver is in each port (the board can read this information for you) and
what each transceiver’s capabilities are.
Using the
fourp
utility in this way will set the respective port's reference clock and reconfigure the FPGA's SERDES
appropriately; however, it will not set up the relevant port’s framing register (
0x800000, 810000, 820000, 830000
Receive Framer Status and Control
0x80003C, 81003C, 82003C, 83003C Demux Bitmask
nor will it enable the relevant channel for DMA in registers
