APPENDIX A: Registers for PCIe8g3 S5
Hardware
EDT, Inc.
2017 January 04
17
APPENDIX A:
Registers for PCIe8g3 S5
For the PCIe8g3 S5 10G/40G, the registers are divided into two main categories and register spaces:
•
the user interface (UI) register space, for functions that are not port-specific; and
•
the port register space, for functions that are port-specific.
Each space contains both indirect and BAR1 memory-mapped registers, and the port register space is further divided
so each port has its own indirect and BAR1 registers. The addresses are shown in
Table
3.
Addresses – UI and port registers (indirect and BAR1 memory-mapped)
The port registers are defined for port 0, and since each of the other ports has identical registers within its respective
memory space, a C macro is included in
edt_stratix5.h
to help you locate a specific register related to a specific
port. The macro, which works for both indirect and BAR1 memory-mapped addresses, is defined as...
STRATIX5_REGXL8(
register_address, port_number
)
...with the italicized variables being replaced by the appropriate register address and port number, as shown in the
access information provided with each register below.
Indirect
BAR1 memory-mapped
UI registers
(non–port-specific)
Any port
0x00–0x7F
0x000000–0x7FFFFF
Port registers
(port-specific)
Port 0
0x80–0x87
0x800000–0x807FFF
Port 1
0x88–0x8F
0x810000–0x817FFF
Port 2
0x90–0x97
0x820000–0x827FFF
Port 3
0x98–0x9F
0x830000–0x837FFF
Port 4
0xA0–0xA7
0x840000–0x847FFF
