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APPENDIX A: Registers for PCIe8g3 S5

Registers, UI

EDT, Inc.

2017 January 04

20

0x10–11 DMA Channel Enable

0x16–17 Least Significant Bit First

0x18–19 Underflow

0x1A–1B Overflow

Access / Notes:

16-bit read-write / SSD16_CHEN

Bit

Access

Name

Description

15–0

RW

CH_ENABLE[15–0]

Set or clear the appropriate bit to enable or reset the corresponding DMA channel:

- Set bit 12 to transmit data to port 4; clear to reset.
- Set bit 11 to transmit data to port 3; clear to reset.
- Set bit 10 to transmit data to port 2; clear to reset.
- Set bit 9 to transmit data to port 1; clear to reset.
- Set bit 8 to transmit data to port 0; clear to reset.
- Set bit 4 to receive data from port 4; clear to reset.
- Set bit 3 to receive data from port 3; clear to reset.
- Set bit 2 to receive data from port 2; clear to reset.
- Set bit 1 to receive data from port 1; clear to reset.
- Set bit 0 to receive data from port 0; clear to reset.

Access / Notes:

16-bit read-write / SSD16_LSB

Registers 0x0D, 0x0F, and 0x16 all can affect how data is ordered.

Bit

Access

Name

Description

15–0

RW

LSB_FIRST[5–0]

When set for a DMA channel, the least significant bit of the 32-bit data word is first, and the most
significant bit is last; when clear, the most significant bit of a 32-bit word is first.

Access / Notes:

16-bit read-only / SSD16_UNDER

Bit

Access

Name

Description

15–0

R only

UNDERFLOW[12 –0]

A value of 1 in a bit indicates that the corresponding DMA channel’s internal FIFO has underflowed
since the channel was last enabled. Underflow causes the corresponding DMA channel to transmit the
last valid byte repeatedly until it receives new DMA data. To reset, clear and reenable the appropriate
channel (see

0x10–11 DMA Channel Enable

).

Access / Notes:

16-bit read-only / SSD16_OVER

Bit

Access

Name

Description

15–0

R only

OVERFLOW[12–0]

A value of 1 in a bit indicates that the corresponding DMA channel’s internal FIFO has overflowed since
the channel was last enabled. Data received while the FIFO is in overflow is discarded. To reset, clear
and reenable the appropriate channel (see

and

0x10–11 DMA Channel Enable

«
...
18
19
20
21
22
...
»

Summary of Contents for PCIe8g3 A5 10G

Page 1: ...User s Guide PCIe8g3 S5 Family PCIe Gen3 x8 boards with Stratix V FPGA and 10G 40G ports Date 2017 January 04 Rev 0001 ...

Page 2: ... 1234 Toll free in U S A 800 435 4320 Fax 1 503 690 1243 www edt com TM TM EDT and Engineering Design Team are trademarks of Engineering Design Team Inc All other trademarks service marks and copyrights are the property of their respective owners 1997 2019 Engineering Design Team Inc All rights reserved ...

Page 3: ...rofits or information and the like arising out of the use or inability to use the Products even if Seller has been advised of the possibility of such damages Because some jurisdictions do not allow the exclusion or limitation of liability for consequential or incidental damages the above limitations may not apply to Buyer Seller s liability to Buyer for actual damages for any cause whatsoever and ...

Page 4: ...ended Configuration 19 0x0F Configuration 19 0x10 11 DMA Channel Enable 20 0x16 17 Least Significant Bit First 20 0x18 19 Underflow 20 0x1A 1B Overflow 20 0x60 62 Extended Indirect Register Address 21 0x63 Extended Indirect Register Data 21 0x64 Serial Master Interface Status 21 0x65 Serial Master Interface Read 7 0 22 0x66 Serial Master Interface Register Address 7 0 22 0x67 Serial Master Interfa...

Page 5: ... Error Count 33 0x800030 810088 820088 830088 Loss of Frame Count 34 0x800034 810034 820034 830034 Pattern Error Count 34 0x80003C 81003C 82003C 83003C Demux Bitmask 35 0x800040 810040 820040 830040 Demux Bitmask Readback 36 0x800060 810060 820060 830060 Detailed Port Status 36 0x800064 810064 820064 830064 Transceiver Reconfiguration Address and Control 36 0x800068 810068 820068 830068 Transceive...

Page 6: ...006C Transceiver Reconfiguration Address and Control 44 0x840074 Frequency Counter Enable 44 0x840078 Receive Frequency Counter 44 0x84007C Transmit Frequency Counter 45 0x840080 PRBS Mode 45 0x840084 PRBS Control 0 45 0x840088 PRBS Control 1 46 0x84008C PRBS Control 2 Reserved 46 0x840090 PRBS Control 3 Reserved 46 0x840094 PRBS Control 4 Reserved 47 Revision Log 48 ...

Page 7: ...r a jitter attenuated recovery clock and A variety of transceiver options Table 1 shows the transceiver options by port for each version Table 1 S5 10G and 40G options by port S5 Port DMA channel Transceiver Wavelength s Signal s 10G 0 0 SFP 1550 1310 850 nm 1GbE OC3 12 48 STM1 4 16 OTU1 SFP 1550 1310 nm 10GbE OC 192 STM64 OTU2 2e 2f SFP 850 nm 10GbE only 1 1 same as port 0 2 2 same as port 0 3 3 ...

Page 8: ...d cautions including those in the EDT provided static discharge kit For links to datasheet specifications and EDT static discharge kit instructions see Related Resources EDT Resources Application programming interface API www edt com api Installation packages Windows Linux Mac www edt com software PCIe8g3 S5 10G datasheet specifications www edt com pcie8g3s5 10g html PCIe8g3 S5 40G datasheet speci...

Page 9: ...om FPGA configuration files can be requested The PCD Device Driver Your EDT installation package contains the PCD device driver the software that runs on the host computer and allows the host operating system to communicate with the S5 The driver is loaded into the kernel at installation and thereafter runs as a kernel module The driver name and subdirectory is specific to each supported operating...

Page 10: ...ribing any EDT board based on Stratix 5 FPGA EdtS5 h Include file for the above C object Edt4P cpp C object describing EDT S5 board Edt4P h Include file for the above C object edt_fourp h Include file In the future the S5 is scheduled to be supported by such additional applications as OCXSnap Example application that captures data from the S5 board and transfers it to disk for testing or verificat...

Page 11: ... if you need to build or rebuild an application run make in that directory Windows users must install a C compiler we recommend the Microsoft Visual C compiler for Windows Linux users can use the gcc compiler typically included with the Linux installation If you use Windows and you wish to use gcc contact tech edt com After you build or rebuild an application use the help command line option for a...

Page 12: ... pcd For Linux or Mac opt EDTpcd 2 At the prompt enter pciload verify to compare the FPGA configuration file in the installation package with the one already loaded in flash memory If multiple boards are installed enter the unit number after the u option pciload u unit number verify If the dates and revision numbers match there is no need to upgrade If they differ you can proceed through the steps...

Page 13: ...s the DDR3 PHY The p 0 flag sets the memory for ports 0 1 2 and 3 The D flag sets the data path for DMA The rx flag sets the data path for receiving data NOTE The D flag always should be used with either the rx or the tx flag rx and tx are mutually exclusive and will affect all ports Initializing Ports Each port can be set up and used independently by using the fourp utility and adding the flags p...

Page 14: ... For 10GbE and 40GbE currently only clear bit data is supported For OTN and OC STM framing headers are included in the data transferred during DMA If framing is enabled the board searches and locks onto incoming SONET SDH frames after detecting the presence of A1 and A2 header patterns at 125 ms intervals The algorithm sequence is 1 Search The board searches for A1 and A2 header patterns until it ...

Page 15: ...ctor external power optional LED for FPGA configuration status Si570 Si570 Si570 Not to scale generic representation only PCIe DMA to from host Port 0 SFP Port 1 SFP Si 5375 FPGA Bank 1 4 GB DDR3 UC time code CPLD LEDs boot select Lemo Si570 Port 2 SFP Port 3 SFP Bank 0 4 GB DDR3 expansion connector external power optional LED for FPGA configuration status Si570 Si570 Si570 Not to scale generic re...

Page 16: ...g properly in all three areas its LED is steady green If not its LED will be blinking Table 2 summarizes the LED behaviors Table 2 LED behaviors LED behavior FPGA receive clock locked ready to receive Signal being received Signal being framed Dim blinking No No No Bright blinking Yes Yes No Bright steady Yes Yes Yes Port 0 TX RX Port 1 TX RX Lemo connector Port 2 TX RX Port 3 TX RX LEDs are enumer...

Page 17: ...t registers are defined for port 0 and since each of the other ports has identical registers within its respective memory space a C macro is included in edt_stratix5 h to help you locate a specific register related to a specific port The macro which works for both indirect and BAR1 memory mapped addresses is defined as STRATIX5_REGXL8 register_address port_number with the italicized variables bein...

Page 18: ... Interrupt bits for the status bits If the corresponding bit is asserted in 0x00 Command then the corresponding bit of these four can be asserted to cause a PCI bus interrupt The PCI bus interrupt then is caused when the corresponding PCD_STAT signal bits 3 0 is asserted To reset the interrupt disable and re enable the appropriate PCD_STAT_INT_EN bit 7 4 in 0x00 Command 3 0 R only PCD_STAT The sta...

Page 19: ...swaps the two 16 bit short words in one 32 bit data word so that short 0 is transferred before short 1 Does not change the order of the bits within each short 2 1 Reserved 0 RW BSWAP Byte swap bit swaps bytes 0 and 1 and also bytes 2 and 3 in a 32 bit data word so that the bytes are positioned 1 0 3 2 Does not change the position of the bits within each byte Below is the structure of a 64 bit data...

Page 20: ...s 0x0D 0x0F and 0x16 all can affect how data is ordered Bit Access Name Description 15 0 RW LSB_FIRST 5 0 When set for a DMA channel the least significant bit of the 32 bit data word is first and the most significant bit is last when clear the most significant bit of a 32 bit word is first Access Notes 16 bit read only SSD16_UNDER Bit Access Name Description 15 0 R only UNDERFLOW 12 0 A value of 1...

Page 21: ...ad write STRATIX5_I2C_DEVICE Bit Access Name Description 7 R only SER_DEV_BSY When set the serial master is busy 6 R only SER_DEV_ACK_ FAIL When set the serial slave failed to respond to the last command 5 0 RW SER_DEV_ADDR Descriptions for devices 0 20 are provided below 0 Port 0 reference clock Si570 1 Port 1 reference clock Si570 2 Ports 2 and 4 reference clock Si570 3 Port 3 reference clock Si...

Page 22: ...ial Master Interface Register Address 15 8 Write the register address on the serial slave that you wish to read Read the register address Access Notes 8 bit read write STRATIX5_I2C_WRITE_DATA Bit Access Name Description 7 0 RW no name This register works bits 7 0 with 0x6A Serial Master Interface Write 15 8 Write data to the serial slave Access Notes 8 bit read write STRATIX5_I2C_READ_DATA_UPPER B...

Page 23: ...ame Assert to reset the external PLL for all four interfaces 6 4 Reserved 3 0 RW no name Set to select the local reference crystal as the source for each respective interface on the external PLL otherwise use the recovered clock as the source Bit 3 Port 3 Bit 2 Port 2 Bit 1 Port 1 Bit 0 Port 0 Access Notes 8 bit read write STRATIX5_SYNC_REG Bit Access Name Description 7 5 Reserved 4 R only STRATIX...

Page 24: ...rite toggle this bit to reset the SPI data path On read when set indicates the input FIFO has overflowed Data may be lost Access Notes 8 bit write only SPI_STROBE Bit Access Name Description 7 0 W only no name Write any value to this register to advance the input FIFO Access Notes 16 bit read only PCD_DESIGN_ID Bit Access Name Description 15 0 R only no name A 16 bit number assigned by the organiz...

Page 25: ...EDT Inc 2017 January 04 25 0x7F Board ID Reserved ...

Page 26: ...ty for memory 13 RW STRATIX5_MEM_ M1_ACTIVE Memory port 1 active 12 RW STRATIX5_M0_ BYPASS Memory port 0 bypass mode 11 R only no name Bank D PHY initialization completed successfully 10 R only no name Bank C PHY initialization completed successfully 9 R only no name Bank B PHY initialization completed successfully 8 R only no name Bank A PHY initialization completed successfully 7 RW no name Bank...

Page 27: ...ank B 100 full 6 R only no name Bank B 75 full 5 R only no name Bank B 50 full 4 R only no name Bank B 25 full 3 R only no name Bank A 100 full 2 R only no name Bank A 75 full 1 R only no name Bank A 50 full 0 R only no name Bank A 25 full Access Notes 32 bit read write STRATIX5_MEMLOOP_LNGTH Bit Access Name Description 31 0 RW no name Memory loop size Access Notes 32 bit read only STRATIX5_MEMINF...

Page 28: ...d 2 RW no name Set for SFP rate select 1 1 RW no name Set for SFP rate select 0 0 RW no name Set to disable transmit Access Notes 8 bit read only 0x82 Port 0 STRATIX5_REGXL8 STRATIX5_PORT_STAT 0 0x8A Port 1 STRATIX5_REGXL8 STRATIX5_PORT_STAT 1 0x92 Port 2 STRATIX5_REGXL8 STRATIX5_PORT_STAT 2 0x9A Port 3 STRATIX5_REGXL8 STRATIX5_PORT_STAT 3 Bit Access Name Description 7 Reserved 6 R only no name Wh...

Page 29: ...Access Notes 8 bit read only 0x87 Port 0 STRATIX5_REGXL8 STRATIX5_PORT_INFO 0 0x8F Port 1 STRATIX5_REGXL8 STRATIX5_PORT_INFO 1 0x97 Port 2 STRATIX5_REGXL8 STRATIX5_PORT_INFO 2 0x9F Port 3 STRATIX5_REGXL8 STRATIX5_PORT_INFO 3 Bit Access Name Description 7 4 R only no name Port type SFP 0 QSFP 1 3 0 R only no name Port number ...

Page 30: ...E_ ALGND When set the framer is byte aligned to the SDH OTN frame alignment signal FAS pattern 8 R only S5_RXFRM_BIT_ ALGND When set the framer is bit aligned to the SDH OTN frame alignment signal FAS pattern 7 5 Reserved 4 RW S5_RXFRM_DIS_ DSCRM Set to disable the descrambler i e acquire framed scrambled data Used only in conjunction with bit 1 S5_RXFRM_EN 3 RW S5_RXFRM_CHK_ PAYLD Set to enable h...

Page 31: ...t 2 STRATIX5_REGXL8 STRATIX5_PORT_RATE 2 0x83000C Port 3 STRATIX5_REGXL8 STRATIX5_PORT_RATE 3 Bit Access Name Description 31 8 Reserved 7 0 RW no name Set expected line rate protocol 0 STM64 OC192 1 STM16 OC48 2 STM4 OC12 3 STM1 OC3 4 1GbE 5 10GbE 6 OTU2 7 OTU2e 8 OTU2F 9 OTU1 Access Notes 32 bit read write 0x800010 Port 0 STRATIX5_REGXL8 STRATIX5_PSYNC_CTRL 0 0x810010 Port 1 STRATIX5_REGXL8 STRAT...

Page 32: ...T_CTRL 3 Bit Access Name Description 31 8 Reserved 7 RW no name Set to enable the frame statistics counters clear to reset the counters 6 1 Reserved 0 RW no name Set to capture frame statistics counter data B1 B2 M1 LOF clear to update counters continuously Access Notes 32 bit read write 0x800018 Port 0 STRATIX5_REGXL8 STRATIX5_TX_NATIONAL 0 0x810018 Port 1 STRATIX5_REGXL8 STRATIX5_TX_NATIONAL 1 0...

Page 33: ...x810024 Port 1 STRATIX5_REGXL8 STRATIX5_B1_ERR_CNT 1 0x820024 Port 2 STRATIX5_REGXL8 STRATIX5_B1_ERR_CNT 2 0x830024 Port 3 STRATIX5_REGXL8 STRATIX5_B1_ERR_CNT 3 Bit Access Name Description 31 24 Reserved 23 0 R only no name The number of B1 bits found to be in error since the counter was last reset Access Notes 32 bit read only 0x800028 Port 0 STRATIX5_REGXL8 STRATIX5_B2_ERR_CNT 0 0x810028 Port 1 ...

Page 34: ...he number of times bit 15 S5_RXFRM_FRM_LCKD in register 0x800000 810000 820000 830000 Receive Framer Status and Control has gone clear Framing is lost when four consecutive bad framing patterns are detected Access Notes 32 bit read only 0x800034 Port 0 STRATIX5_REGXL8 STRATIX5_PAT_ERR_CNT 0 0x810034 Port 1 STRATIX5_REGXL8 STRATIX5_PAT_ERR_CNT 1 0x820034 Port 2 STRATIX5_REGXL8 STRATIX5_PAT_ERR_CNT ...

Page 35: ...s 0 11 of the mask are used Example To select AU 4 1 0 the first STM1 use the pdb commands wm132 80003C 80000007 wm132 80003C 80000107 wm132 80003C 80000207 or to select AU 3 1 1 the first AU 3 use the commands wm132 80003C 80000007 wm132 80003C 8000010F wm132 80003C 8000020F The mask is written 4 bits at a time only the first 48 bits 0 47 of the mask are used Example To select AU 4 1 1 0 the firs...

Page 36: ..._REGXL8 STRATIX5_PORT_STAT2 0 0x810060 Port 1 STRATIX5_REGXL8 STRATIX5_PORT_STAT2 1 0x820060 Port 2 STRATIX5_REGXL8 STRATIX5_PORT_STAT2 2 0x830060 Port 3 STRATIX5_REGXL8 STRATIX5_PORT_STAT2 3 Bit Access Name Description 31 2 Reserved 1 R only no name Lane 0 transceiver clock and data recovery CDR is locked to data 0 R only no name Lane 0 transceiver clock and data recovery CDR is locked to referen...

Page 37: ...XCVR_MGMT_RDATA 0 0x81006C Port 1 STRATIX5_REGXL8 STRATIX5_XCVR_MGMT_RDATA 1 0x82006C Port 2 STRATIX5_REGXL8 STRATIX5_XCVR_MGMT_RDATA 2 0x83006C Port 3 STRATIX5_REGXL8 STRATIX5_XCVR_MGMT_RDATA 3 Bit Access Name Description 31 0 R only no name Reconfiguration interface read data Access Notes 32 bit read write 0x800074 Port 0 STRATIX5_REGXL8 STRATIX5_FREQ_CNT_EN 0 0x810074 Port 1 STRATIX5_REGXL8 STR...

Page 38: ...STRATIX5_PORT_PRBS_MODE 3 Bit Access Name Description 31 8 Reserved 7 0 RW no name PRBS mode Access Notes 32 bit read write 0x800084 Port 0 STRATIX5_REGXL8 STRATIX5_PORT_PRBS_CTRL0 0 0x810084 Port 1 STRATIX5_REGXL8 STRATIX5_PORT_PRBS_CTRL0 1 0x820084 Port 2 STRATIX5_REGXL8 STRATIX5_PORT_PRBS_CTRL0 2 0x830084 Port 3 STRATIX5_REGXL8 STRATIX5_PORT_PRBS_CTRL0 3 Bit Access Name Description 31 Reserved ...

Page 39: ...88 Port 3 STRATIX5_REGXL8 STRATIX5_PORT_PRBS_CTRL1 3 Bit Access Name Description 31 Reserved 30 R only no name Lane 3 transmit PRBS realtime error 29 R only no name Lane 3 transmit PRBS latched error 28 R only no name Lane 3 transmit PRBS synchronized 27 26 Reserved 25 RW no name Lane 3 transmit PRBS check enable 24 RW no name Lane 3 transmit PRBS generate enable 23 Reserved 22 R only no name Lane...

Page 40: ...08C 82008C 83008C PRBS Control 2 Reserved 0x800090 810090 820090 830090 PRBS Control 3 Reserved 0x800094 810094 820094 830094 PRBS Control 4 Reserved 4 R only no name Lane 2 receive PRBS synchronized 3 2 Reserved 1 RW no name Lane 2 receive PRBS check enable 0 RW no name Lane 2 receive PRBS generate enable ...

Page 41: ...ccess Notes 8 bit read write STRATIX5_REGXL8 STRATIX5_PORT_CTRL 4 Bit Access Name Description 7 3 Reserved 2 RW no name Set to enable PLL1 not used 1 RW no name Set to enable PLL0 not used 0 RW no name Set to enable the LIU not used Access Notes 8 bit read only STRATIX5_REGXL8 STRATIX5_PORT_STAT 4 Bit Access Name Description 7 Reserved 6 R only no name When set indicates the transceiver reconfigur...

Page 42: ... Registers Port Port 4 QSFP EDT Inc 2017 January 04 42 0xA7 Port Information Access Notes 8 bit read only STRATIX5_REGXL8 STRATIX5_PORT_INFO 4 Bit Access Name Description 7 4 R only no name Port type QSFP 1 3 0 R only no name Port number ...

Page 43: ...its to transmit until the selected threshold is reached 11 10 Reserved 9 8 RW no name Select transmit trigger source 0 external 1 internal 7 RW STRATIX5_ RXTRIG_ARM Set to arm receive trigger 6 3 Reserved 2 RW no name Set to disable wait for frame receive trigger mode 1 0 RW no name Select receive trigger source 0 external 1 internal Access Notes 32 bit read only STRATIX5_REGXL8 STRATIX5_PORT_STAT...

Page 44: ...Access Name Description 31 19 Reserved 18 RW no name Caution This bit affects all ports Set to reset the entire FPGA transceiver reconfiguration interface 17 R only no name Set when the transceiver reconfiguration interface is busy 16 RW no name Set to reset the port s transceiver 15 0 RW no name Reconfiguration register address Access Notes 32 bit read write STRATIX5_REGXL8 STRATIX5_XCVR_MGMT_WDA...

Page 45: ...ransmit PRBS latched error 28 R only no name Lane 1 transmit PRBS synchronized 27 26 Reserved 25 RW no name Lane 1 transmit PRBS check enable 24 RW no name Lane 1 transmit PRBS generate enable 23 Reserved 22 R only no name Lane 1 receive PRBS realtime error 21 R only no name Lane 1 receive PRBS latched error 20 R only no name Lane 1 receive PRBS synchronized 19 18 Reserved 17 RW no name Lane 1 rec...

Page 46: ... Lane 3 transmit PRBS generate enable 23 Reserved 22 R only no name Lane 3 receive PRBS realtime error 21 R only no name Lane 3 receive PRBS latched error 20 R only no name Lane 3 receive PRBS synchronization 19 18 RW no name Reserved 17 RW no name Lane 3 receive PRBS check enable 16 RW no name Lane 3 receive PRBS generate enable 15 Reserved 14 R only no name Lane 2 transmit PRBS realtime error 13...

Page 47: ...APPENDIX A Registers for PCIe8g3 S5 Registers Port Port 4 QSFP EDT Inc 2017 January 04 47 0x840094 PRBS Control 4 Reserved ...

Page 48: ... Log EDT Inc 2017 January 04 48 Revision Log Below is a history of modifications to this guide Date By Rev Pg s Detail 20170104 PH RH 0001 4 Corrected www edt com downloads api to www edt com api 20140730 PH SB TL 0000 All Created this new guide ...

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