Hardware Description
2-6
TSEV81102G0FS Evaluation Board User Guide
0974C–BDC–02/09
e2v semiconductors SAS 2009
2.5
Output Access
2.5.1
Digital Outputs
Access to the single-ended output data and to the differential output clock (A[0..9] to
H[0..9], RefA to RefH, DR, DRb) is provided by male 2.54 mm pitch connectors, via 60
Ω
microstrip lines. The microstrip lines are 50
Ω
terminated.
The connectors are made up of two rows of pitches. The upper row is used for the signal
connections. The lower row is connected to GND. The output ports are separated from
one another by a column (two pitches) connected to GND, as shown:
Figure 2-7.
Output Data Pitch Connector
Note:
The characteristic impedance of the data output microstrip lines is 60
Ω
so as to termi-
nate the lines by either 50
Ω
(ECL, PECL output format) or 75
Ω
(TTL output format,
available on request only).
2.5.2
ADC
Synchronization
Output Signal
Access
Access to the differential signal
ADCDelAdjOut
/
ADCDelAdjOutb
is provided by two SMA
connectors, via 50
Ω
microstrip lines.
2.6
DMUX Function
Settings
Four 2 mm section banana jacks are provided to perform die temperature measure-
ments (see Section 5.3).
Three potentiometers are provided for the adjustment of
SWIADJ
,
ADCDelAdCtrl
and
DMUXDelAdjCtrl
respectively.
Four jumpers are provided for the settings of the static control signals
NBBIT
,
RATIO-
SEL
,
CLKINTYPE
and
BIST
(jumper on = logic '0', jumper off = logic '1').
2.7
Layout
Information
The DMUX processes high-frequency signals and as such particular attention was given
to the board’s layout to achieve full-speed operation efficiency. The length of the trans-
mission lines for both the input and output signals have been matched. In addition,
cross-talk effects for the output data have been reduced by increasing, wherever possi-
ble, the space between the lines.
Note:
It is recommended to route the input data with differential lines whenever possible.
2.7.1
Decoupling of Power
Supplies
Each power supply is decoupled by a 1 µF tantalum capacitor in parallel to a 100 nF
chip capacitor.
Each power supply access of the DMUX is bypassed as close as possible to the device
by 10 nF and 100 pF surface mount chip capacitors side by side.
Note:
These capacitors are superimposed with the capacitor of lowest value soldered first.
2.7.2
Reference Planes
Each reference plane (layers 3 and 7) is physically divided into two parts: one GND
plane and one V
PLUSD
plane, which is the voltage reference for the output buffers of the
GND GND GND GND GND
GND GND GND
X9 GND RefY
Y1 Y2
Y9 GND RefZ
