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TSEV81102G0FS Evaluation Board User Guide

0974C–BDC–02/09

e2v semiconductors SAS 2009

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Summary of Contents for TSEV81102G0FS

Page 1: ...TSEV81102G0FS Evaluation Board User Guide...

Page 2: ......

Page 3: ...Supplies and Ground Access 2 5 2 4 Input Access 2 5 2 4 1 Input Data and Clock Access 2 5 2 4 2 Synchronous Reset Access 2 5 2 4 3 Asynchronous Reset Access 2 5 2 4 4 ADC Synchronization Input Signal...

Page 4: ...MUX Setting 4 2 4 4 BIST 4 3 4 5 Delay Adjust Function 4 3 4 6 Die Junction Temperature Monitoring 4 4 4 7 Applying the TSEV81102G0FS DMUX to e2v ADC Evaluation Boards 4 4 4 8 Miscellaneous 4 5 Sectio...

Page 5: ...nnection to e2v s ADC Evaluation Boards for example TSEV8388BGL and TSEV83102G0BGL for an extended functionality evaluation ADC and DMUX multi channel applications The DMUX EB is delivered fully assem...

Page 6: ...Introduction 1 2 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 7: ...X in a CQFP 196 package is in fact a cavity up device while the DMUX in TBGA 240 is a cavity down device Consequently all signals on the DMUX in a CQFP package are mirror images of the ones on the DMU...

Page 8: ...LZA2 and TSEV83102G0BGL ADC Boards Figure 2 4 TSEV81102G0FS Board to ADC Board Connection TSEV8388GL GLZA2 and TSEV83102G0BGL Simplified Diagram GND GND Ix Ixb GND DMUX Evaluation Board Component Side...

Page 9: ...Single VCC Power Supplies Temperature Measruments Power Supplies VEE VPLUSD VTT BANANA JACKS 2 mm PITCH CONNECTOR 2 54 mm IGND VDIODE VGND SUBVIS Connector SMA Connectors Async Reset Single Sync Rese...

Page 10: ...s 4 and 6 Considering the severe mechanical constraints of the wide temperature range and the high frequency domain in which the board is meant to operate two different dielectric materials are used T...

Page 11: ...ccess 2 4 1 Input Data and Clock Access Access to the differential data and clock inputs Clkln Clklnb I 0 9 I 0 9 b are pro vided by a 2 54 mm female pitch connector via 50 microstrip lines The connec...

Page 12: ...rs are provided for the adjustment of SWIADJ ADCDelAdCtrl and DMUXDelAdjCtrl respectively Four jumpers are provided for the settings of the static control signals NBBIT RATIO SEL CLKINTYPE and BIST ju...

Page 13: ...1 ps inch Table 2 2 I O Transmission Lines Signal Type Typical length Length Matching Characteristic impedance Adaptation Comments ClkInClkInb Differential 68 2 mm 68 2 mm 50 On chip 100 differential...

Page 14: ...Hardware Description 2 8 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 15: ...ote One can set the DMUX to several other output formats as long as the buffer output cur rent remains below 36 mA and VPLUSD stays below 4V with VPLUSD VEE 8 3V The output levels are thus given by th...

Page 16: ...to 4 V Analog input voltages ADCDelAdjCtrl ADCDelAdjCtrlb DMUXDelAdjCtrl DMUXDelAdjCtrlb SwiAdj Voltage range for each pad Differential voltage range 1 to 1 V ECL 50 input voltage Clkln ClklnbI 0 9 I...

Page 17: ...ns Parameter Symbol Comments Min Typ Max Unit Positive supply voltage VCC 4 75 5 5 25 V Positive output buffer supply voltage VPLUSD ECL output compatibility 0 0 0 V PECL output compatibility 3 13 3 3...

Page 18: ...Operating Characteristics 3 4 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 19: ...rd for the first time It describes the step by step process you must follow to accomplish a BIST sequence Built In Self Test see Section 4 4 in order to verify if the board is functional At the end of...

Page 20: ...d SWIADJ so that the SWIADJ pin of the DMUX is at 0V 11 Apply the ASYNCRESET by pressing the corresponding button to start the DMUX the ASYNCRESET signal is active at high TTL level At the output the...

Page 21: ...be set to logic 1 jumper out The following figure shows the BIST sequence Figure 4 1 BIST Sequence Note The complete BIST sequence is available on request 4 5 Delay Adjust Function Two delay adjusts...

Page 22: ...2G0B ADC evaluation boards Figure 4 4 on page 5 shows the ADC and DMUX board connections and Table 4 2 pro vides the required configuration to match the DMUX board with the ADC board When used with th...

Page 23: ...102G0BGL TSEV81102G0FS Device at the Bottom D0 I0 D0 I0 D1 I1 D1 I1 D2 I2 D2 I2 D3 I3 D3 I3 D4 I4 D4 I4 D5 I5 D5 I5 D6 I6 D6 I6 D7 I7 D7 I7 I8 not connected D8 I8 if applicable I9 not connected D9 I9...

Page 24: ...semiconductors SAS 2009 Always make sure the output current through the termination resistors does not exceed 36 mA After the supplies are switched on send an asynchronous reset pulse into the DMUX i...

Page 25: ...118 128 146 147 Ground Analog Input Signals DMUXDelAdjCtrl 194 In phase DMUX clock delay cell control signal DMUXDelAdjCtrlB 195 Inverted phase DMUX clock delay cell control signal ADCDelAdjCtrl 47 I...

Page 26: ...data RefA to RefH 178 55 164 70 149 84 129 103 Reference outputs tied to the common mode voltage of each port DR 125 In phase data ready signal centered on the output data frequency output data 2 DRB...

Page 27: ...Package Description TSEV81102G0FS Evaluation Board User Guide 5 3 0974C BDC 02 09 5 2 Enhanced CQFP 196 Pinout Figure 5 1 CQFP 196 Package Pinout Top View...

Page 28: ...eads Kovar Ni and Au plating Lid Kovar Ni and Au plating Heat spreader on the bottom CuW with Ni and Au plating Figure 5 2 CQFP 196 Package Top View 18 54 mm 18 54 mm Pin 1 Index 0 230 mm 0 050 0 038...

Page 29: ...0 20 0 50 0 51 mm 0 200 mm 0 150 mm 22 86 mm2 Thermal Resistance Junction to bottom of case 0 26 0 31 1 44 0 07 0 07 2 15 C Watt customer thermal interface excluded Estimated Thermal Model For 196 CQF...

Page 30: ...Package Description 5 6 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 31: ...tion Part Number Package Temperature Range Screening Comments TS81102G0VFS CQFP 196 V grade 40 C Tc Tj 110 C Standard Contact e2v sales TS81102G0MFS CQFP 196 M grade 55 C Tc Tj 125 C MIL Contact e2v s...

Page 32: ...Ordering Information 6 2 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 33: ...TSEV81102G0FS Evaluation Board User Guide 7 1 0974C BDC 02 09 e2v semiconductors SAS 2009 Section 7 Appendices...

Page 34: ...7 2 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009 7 1 Electrical Schematics Figure 7 1 TSEV81102G0FS Electrical Schematics...

Page 35: ...TSEV81102G0FS Evaluation Board User Guide 7 3 0974C BDC 02 09 Figure 7 2 TSEV81102G0FS Component Layer Top Figure 7 3 TSEV81102G0FS Component Layer Bottom...

Page 36: ...7 4 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009 Figure 7 4 TSEV81102G0FS Top Layer Figure 7 5 TSEV81102G0FS Second Layer GND and VPLUSD...

Page 37: ...TSEV81102G0FS Evaluation Board User Guide 7 5 0974C BDC 02 09 Figure 7 6 TSEV81102G0FS Third Layer GND and Power Supplies Figure 7 7 TSEV81102G0FS Fourth Layer GND VPLUSD and Miscellaneous...

Page 38: ...7 6 TSEV81102G0FS Evaluation Board User Guide 0974C BDC 02 09 e2v semiconductors SAS 2009...

Page 39: ...Waterhouse Lane Chelmsford Essex CM1 2QU England Tel 44 0 1245 493493 Fax 44 0 1245 492492 mailto enquiries e2v com e2v sas 16 Burospace F 91572 Bi vres Cedex France Tel 33 0 16019 5500 Fax 33 0 1601...

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