Application Information
TSEV81102G0FS Evaluation Board User Guide
4-3
0974C–BDC–02/09
4.4
BIST
The bist sequence is a 10-bit 512-code pseudo-random sequence defined by the follow-
ing equation:
with N(0) = 2 and i
0
= 1
The sequence starts on port A. The driving clock during the BIST sequence is CLKIN.
Depending on the selected ratio, the BIST can be seen on ports A to H (1:8 ratio) or on
ports A to D (1:4 ratio).
Since the BIST is a 10-bit sequence, we recommend setting the NBBIT signal to logic
“1” for 10-bit mode (jumper out).
CLKINTYPE must be set to logic “1” (jumper out).
The following figure shows the BIST sequence.
Figure 4-1.
BIST Sequence
Note:
The complete BIST sequence is available on request.
4.5
Delay Adjust
Function
Two delay adjusts of ±250 ps controlled by potentiometers are available to synchronize
the input clock and the DMUX data on the one hand, and delay the signal
ADCDelAdjIn
on the other.
The input signal
DelAdjCtrl
is tied to GND.
The input signal
DelAdjCtrlb
can vary from -0.55V to 0.55V, depending on the
potentiometer position.
The generated delay is proportional to the differential across
DelAdjCtrl
and
N i
( )
2
N i
1
–
(
)
×
int
N i
1
–
(
)
256
--------------------
⎝
⎛
⎠
⎞
+
%2
int
N i
1
–
(
)
16
--------------------
⎝
⎠
⎛
⎞
%2
%2
+
%1024
=
0
256
512
768
1024
0
32
64
96
128 160 192 224 256 288 320 352 384 416 448 480 512
Samples
Code
