Hardware Description
TSEV81102G0FS Evaluation Board User Guide
2-7
0974C–BDC–02/09
DMUX. V
PLUSD
can be set to all levels between GND and 3.3V, allowing the DMUX to be
set in various output modes (ECL with V
PLUSD
= GND, PECL with V
PLUSD
= 3.3V, etc.).
2.7.3
I/O Transmission
Lines
Table 2-2 summarizes the main properties of the microstrip lines of all the input and out-
put signals.
Note:
The transmission delay through a transmission line is approximately 6.1 ps/inch.
Table 2-2.
I/O Transmission Lines
Signal
Type
Typical
length
Length
Matching
Characteristic
impedance
Adaptation
Comments
ClkInClkInb
Differential
68.2 mm
68.2 mm
--
50
Ω
On-chip 100
Ω
differential
I[0..9], I[0..9]b
Differential
68.9 mm
±1
50
Ω
On-chip 100
Ω
differential
Min. length (I1B): 68.3 mm
Max length (I0B): 69.6 mm
A[0..9], …,
H[0..9]
Single-
ended
120 mm
±8
60
Ω
50
Ω
Min. length (F3 & E5):112 mm
Max length (C9): 127.9 mm
DRDRb
Differential
113.5 mm
113.5 mm
-
60
Ω
50
Ω
SyncResetSync
Resetb
Differential
85.7 mm
±1
50
Ω
On-chip 100
Ω
differential
ADCDelAdjInAD
CDelAdjInb
Differential
100 mm
±1
50
Ω
On-chip 100
Ω
differential
ADCDelAdjOut
ADCDelAdjOutb
Differential
106 mm
±1
50
Ω
None
